edaBits, ChaiGear, TopGear, CCD.

BMR/Register.h

@@ -233,6 +233,8 @@ class Phase
 	template <class T>
 	static void ands(T& processor, const vector<int>& args) { processor.ands(args); }
 	template <class T>
+	static void xors(T& processor, const vector<int>& args) { processor.xors(args); }
+	template <class T>
 	static void inputb(T& processor, const vector<int>& args) { processor.input(args); }
 	template <class T>
 	static T get_input(int from, GC::Processor<T>& processor, int n_bits)

BMR/common.h

@@ -11,6 +11,8 @@
 #include <vector>
 using namespace std;
 
+#include "Tools/CheckVector.h"
+
 typedef unsigned long wire_id_t;
 typedef unsigned long gate_id_t;
 typedef unsigned int party_id_t;
@@ -37,20 +39,4 @@ class Function {
 	bool call(bool left, bool right) { return rep[2 * left + right]; }
 };
 
-template <class T>
-class CheckVector : public vector<T>
-{
-public:
-	CheckVector() : vector<T>() {}
-	CheckVector(size_t size) : vector<T>(size) {}
-	CheckVector(size_t size, const T& def) : vector<T>(size, def) {}
-#ifdef CHECK_SIZE
-	T& operator[](size_t i) { return this->at(i); }
-	const T& operator[](size_t i) const { return this->at(i); }
-#else
-	T& at(size_t i) { return (*this)[i]; }
-	const T& at(size_t i) const { return (*this)[i]; }
-#endif
-};
-
 #endif /* CIRCUIT_INC_COMMON_H_ */

CHANGELOG.md

@@ -1,5 +1,17 @@
 The changelog explains changes pulled through from the private development repository. Bug fixes and small enhancements are committed between releases and not documented here.
 
+## 0.1.5 (Mar 20, 2020)
+
+- Faster conversion between arithmetic and binary secret sharing using [extended daBits](https://eprint.iacr.org/2020/338)
+- Optimized daBits
+- Optimized logistic regression
+- Faster compilation of repetitive code (compiler option `-C`)
+- ChaiGear: [HighGear](https://eprint.iacr.org/2017/1230) with covert key generation
+- [TopGear](https://eprint.iacr.org/2019/035) zero-knowledge proofs
+- Binary computation based on Shamir secret sharing
+- Fixed security bug: Prove correctness of ciphertexts in input tuple generation
+- Fixed security bug: Missing check in MASCOT bit generation and various binary computations
+
 ## 0.1.4 (Dec 23, 2019)
 
 - Mixed circuit computation with secret sharing

Compiler/GC/instructions.py

@@ -36,6 +36,8 @@ class ClearBitsAF(base.RegisterArgFormat):
     STMSBI = 0x243,
     MOVSB = 0x244,
     INPUTB = 0x246,
+    SPLIT = 0x248,
+    CONVCBIT2S = 0x249,
     XORCBI = 0x210,
     BITDECC = 0x211,
     CONVCINT = 0x213,
@@ -49,15 +51,23 @@ class ClearBitsAF(base.RegisterArgFormat):
     MULCBI = 0x21c,
     SHRCBI = 0x21d,
     SHLCBI = 0x21e,
+    CONVCINTVEC = 0x21f,
     PRINTREGSIGNED = 0x220,
     PRINTREGB = 0x221,
     PRINTREGPLAINB = 0x222,
     PRINTFLOATPLAINB = 0x223,
     CONDPRINTSTRB = 0x224,
     CONVCBIT = 0x230,
+    CONVCBITVEC = 0x231,
 )
 
-class xors(base.Instruction):
+class BinaryVectorInstruction(base.Instruction):
+    is_vec = lambda self: True
+
+    def copy(self, size, subs):
+        return type(self)(*self.get_new_args(size, subs))
+
+class xors(BinaryVectorInstruction):
     code = opcodes['XORS']
     arg_format = tools.cycle(['int','sbw','sb','sb'])
 
@@ -73,15 +83,21 @@ class xorcbi(base.Instruction):
     code = opcodes['XORCBI']
     arg_format = ['cbw','cb','int']
 
-class andrs(base.Instruction):
+class andrs(BinaryVectorInstruction):
     code = opcodes['ANDRS']
     arg_format = tools.cycle(['int','sbw','sb','sb'])
 
-class ands(base.Instruction):
+    def add_usage(self, req_node):
+        req_node.increment(('bit', 'triple'), sum(self.args[::4]))
+
+class ands(BinaryVectorInstruction):
     code = opcodes['ANDS']
     arg_format = tools.cycle(['int','sbw','sb','sb'])
 
-class andm(base.Instruction):
+    def add_usage(self, req_node):
+        req_node.increment(('bit', 'triple'), sum(self.args[::4]))
+
+class andm(BinaryVectorInstruction):
     code = opcodes['ANDM']
     arg_format = ['int','sbw','sb','cb']
 
@@ -181,6 +197,31 @@ class convcbit(base.Instruction):
     code = opcodes['CONVCBIT']
     arg_format = ['ciw','cb']
 
+@base.vectorize
+class convcintvec(base.Instruction):
+    code = opcodes['CONVCINTVEC']
+    arg_format = tools.chain(['c'], tools.cycle(['cbw']))
+
+class convcbitvec(BinaryVectorInstruction):
+    code = opcodes['CONVCBITVEC']
+    arg_format = ['int','ciw','cb']
+    def __init__(self, *args):
+        super(convcbitvec, self).__init__(*args)
+        assert(args[2].n == args[0])
+        args[1].set_size(args[0])
+
+class convcbit2s(BinaryVectorInstruction):
+    code = opcodes['CONVCBIT2S']
+    arg_format = ['int','sbw','cb']
+
+@base.vectorize
+class split(base.Instruction):
+    code = opcodes['SPLIT']
+    arg_format = tools.chain(['int','s'], tools.cycle(['sbw']))
+    def __init__(self, *args, **kwargs):
+        super(split_class, self).__init__(*args, **kwargs)
+        assert (len(args) - 2) % args[0] == 0
+
 class movsb(base.Instruction):
     code = opcodes['MOVSB']
     arg_format = ['sbw','sb']
@@ -196,9 +237,9 @@ class bitb(base.Instruction):
     code = opcodes['BITB']
     arg_format = ['sbw']
 
-class reveal(base.Instruction):
+class reveal(BinaryVectorInstruction, base.VarArgsInstruction, base.Mergeable):
     code = opcodes['REVEAL']
-    arg_format = ['int','cbw','sb']
+    arg_format = tools.cycle(['int','cbw','sb'])
 
 class inputb(base.DoNotEliminateInstruction, base.VarArgsInstruction):
     __slots__ = []