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Add unratified Smclic, Ssclic, Smclicshv extensions
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| /*=======================================================================================*/ | ||
| /* This Sail RISC-V architecture model, comprising all files and */ | ||
| /* directories except where otherwise noted is subject the BSD */ | ||
| /* two-clause license in the LICENSE file. */ | ||
| /* */ | ||
| /* SPDX-License-Identifier: BSD-2-Clause */ | ||
| /*=======================================================================================*/ | ||
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| val vector_table_fetch : xlenbits -> VectorTableFetchResult | ||
| function vector_table_fetch(table_addr) -> VectorTableFetchResult = | ||
| if sizeof(xlen) == 32 then { | ||
| match mem_read(Execute(), table_addr, 4, false, false, false) { | ||
| MemException(e) => F_TableError(e, table_addr), | ||
| MemValue(table_entry) => F_TableEntry(table_entry) | ||
| } | ||
| } else { /* xlen == 64 */ | ||
| match mem_read(Execute(), table_addr, 8, false, false, false) { | ||
| MemException(e) => F_TableError(e, table_addr), | ||
| MemValue(table_entry) => F_TableEntry(table_entry) | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,95 @@ | ||
| /*=======================================================================================*/ | ||
| /* This Sail RISC-V architecture model, comprising all files and */ | ||
| /* directories except where otherwise noted is subject the BSD */ | ||
| /* two-clause license in the LICENSE file. */ | ||
| /* */ | ||
| /* SPDX-License-Identifier: BSD-2-Clause */ | ||
| /*=======================================================================================*/ | ||
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| /* Architectural state for the 'Smclic' fast interrupts extension. */ | ||
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| /* Smclic csrs */ | ||
| mapping clause csr_name_map = 0x307 <-> "mtvt" | ||
| mapping clause csr_name_map = 0x345 <-> "mnxti" | ||
| mapping clause csr_name_map = 0xFB1 <-> "mintstatus" | ||
| mapping clause csr_name_map = 0x347 <-> "mintthresh" | ||
| mapping clause csr_name_map = 0x348 <-> "mscratchcsw" | ||
| mapping clause csr_name_map = 0x349 <-> "mscratchcswl" | ||
| /* Ssclic csrs */ | ||
| mapping clause csr_name_map = 0x107 <-> "stvt" | ||
| mapping clause csr_name_map = 0x145 <-> "snxti" | ||
| mapping clause csr_name_map = 0xDB1 <-> "sintstatus" | ||
| mapping clause csr_name_map = 0x147 <-> "sintthresh" | ||
| mapping clause csr_name_map = 0x148 <-> "sscratchcsw" | ||
| mapping clause csr_name_map = 0x149 <-> "sscratchcswl" | ||
| /* Suclic csrs */ | ||
| mapping clause csr_name_map = 0x107 <-> "utvt" | ||
| mapping clause csr_name_map = 0x145 <-> "unxti" | ||
| mapping clause csr_name_map = 0xDB1 <-> "uintstatus" | ||
| mapping clause csr_name_map = 0x147 <-> "uintthresh" | ||
| mapping clause csr_name_map = 0x148 <-> "sscratchcsw" | ||
| mapping clause csr_name_map = 0x149 <-> "sscratchcswl" | ||
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| register inhv : bits(1) /* internal state of accessing vector table, exception handler will decide which xinhv to set */ | ||
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| register mtvt : xlenbits | ||
| register mintthresh : ilbits | ||
| register mil : ilbits | ||
| register mpil : ilbits | ||
| register minhv : bits(1) | ||
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| register stvt : xlenbits | ||
| register sintthresh : ilbits | ||
| register sil : ilbits | ||
| register spil : ilbits | ||
| register sinhv : bits(1) | ||
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| register utvt : xlenbits | ||
| register uintthresh : ilbits | ||
| register uil : ilbits | ||
| register upil : ilbits | ||
| register uinhv : bits(1) | ||
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| register clicintip_raw : vector(4096, dec, bits(1)) | ||
| register clicintip_raw_prev : vector(4096, dec, bits(1)) | ||
| register clicintip : vector(4096, dec, bits(1)) | ||
| register clicintie : vector(4096, dec, bits(1)) | ||
| register clicintctl : vector(4096, dec, ilbits) | ||
| register clicintattr : vector(4096, dec, clicintattr_layout) | ||
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| bitfield ClicMcause : xlenbits = { | ||
| IsInterrupt : xlen - 1, | ||
| Minhv : 30, | ||
| ClicMcauseMpp : 29 .. 28, | ||
| ClicMcauseMpie: 27, | ||
| Mpil : 23 .. 16, | ||
| Exccode : 11 .. 0 | ||
| } | ||
| register clicmcause : ClicMcause | ||
| register clicmstatus : Mstatus | ||
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| bitfield ClicScause : xlenbits = { | ||
| IsInterrupt : xlen - 1, | ||
| Sinhv : 30, | ||
| ClicScauseSpp : 28, | ||
| ClicScauseSpie: 27, | ||
| Spil : 23 .. 16, | ||
| Exccode : 11 .. 0 | ||
| } | ||
| register clicscause : ClicScause | ||
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| bitfield ClicUcause : xlenbits = { | ||
| IsInterrupt : xlen - 1, | ||
| Uinhv : 30, | ||
| ClicUcauseUpie: 27, | ||
| Upil : 23 .. 16, | ||
| Exccode : 11 .. 0 | ||
| } | ||
| register clicucause : ClicUcause | ||
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| bitfield Mintstatus : xlenbits = { | ||
| mil : 31 .. 24, | ||
| sil : 15 .. 8, | ||
| uil : 7 .. 0 | ||
| } | ||
| register mintstatus : Mintstatus |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,36 @@ | ||
| /*=======================================================================================*/ | ||
| /* This Sail RISC-V architecture model, comprising all files and */ | ||
| /* directories except where otherwise noted is subject the BSD */ | ||
| /* two-clause license in the LICENSE file. */ | ||
| /* */ | ||
| /* SPDX-License-Identifier: BSD-2-Clause */ | ||
| /*=======================================================================================*/ | ||
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| /* Definitions for fast interrupt (Smclic extensions) */ | ||
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| /* default register type */ | ||
| type ilbits = bits(8) | ||
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| bitfield clicintattr_layout : bits(8) = { | ||
| MODE : 7 .. 6, /* privilege mode */ | ||
| TRIG : 2 .. 1, /* 11 - negedge triggered */ | ||
| /* 10 - active low */ | ||
| /* 01 - posedge triggered */ | ||
| /* 00 - active high */ | ||
| SHV : 0 /* hardware vectored interrupt */ | ||
| } | ||
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| val is_shv : bitvector(1) -> bool | ||
| function is_shv (shv) = | ||
| match (shv) { | ||
| 0b0 => false, | ||
| 0b1 => true | ||
| } | ||
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| let CLIC_MTI = 7 | ||
| let CLIC_MSI = 3 | ||
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| union VectorTableFetchResult = { | ||
| F_TableEntry : xlenbits, /* Entry in vector table */ | ||
| F_TableError : (ExceptionType, xlenbits) /* standard exception and table entry addr */ | ||
| } |
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