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Polish tests
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 * finally fix ALU example so it doesn't mistake addition for subtration
 * use the proper topEntity in IntegralTB
 * don't do `done' = not <$> done`, is just confusing
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@leonschoorl
leonschoorl committed Nov 12, 2021
1 parent 1352c52 commit bda049d
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Showing 6 changed files with 36 additions and 36 deletions.
4 changes: 2 additions & 2 deletions examples/ALU.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,6 @@ import Clash.Prelude
data OPC = ADD | MUL | SUB

topEntity :: OPC -> Integer -> Integer -> Integer
topEntity SUB = (+)
topEntity ADD = (-)
topEntity SUB = (-)
topEntity ADD = (+)
topEntity MUL = (*)
2 changes: 1 addition & 1 deletion tests/Main.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -289,7 +289,7 @@ runClashTest = defaultMain $ clashTestRoot
}
, runTest "RecursiveBoxed" def{
hdlTargets=[VHDL]
, expectClashFail=Just (def, " already inlined 20 times in: RecursiveBoxed.topEntity")
, expectClashFail=Just (def, " already inlined 20 times in: ") -- (RecursiveBoxed\.)?topEntity
}
, runTest "RecursiveDatatype" def{
hdlTargets=[VHDL]
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28 changes: 14 additions & 14 deletions tests/shouldwork/DDR/DDRin.hs
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Expand Up @@ -79,11 +79,11 @@ testBenchUS = done
expectedOutput = outputVerifier clkTest rstTest testoutputSync
actualOutput = ignoreFor clkReal rstReal enableGen d1 (dummy, dummy) (topEntityUS clkReal rstReal testInput)
done = expectedOutput actualOutput
done' = not <$> done
notDone = not <$> done

clkTest = tbClockGen @TB done'
clkDDR = tbClockGen @SyncDDR (unsafeSynchronizer clkTest clkDDR done')
clkReal = tbClockGen @SyncReal (unsafeSynchronizer clkTest clkReal done')
clkTest = tbClockGen @TB notDone
clkDDR = tbClockGen @SyncDDR (unsafeSynchronizer clkTest clkDDR notDone)
clkReal = tbClockGen @SyncReal (unsafeSynchronizer clkTest clkReal notDone)

rstTest = resetGen @TB
rstDDR = resetGen @SyncDDR
Expand All @@ -96,10 +96,10 @@ testBenchUA = done
expectedOutput = outputVerifier' clkReal rstReal testoutputAsync
actualOutput = ignoreFor clkReal rstReal enableGen d1 (dummy, dummy) (topEntityUA clkReal rstReal testInput)
done = expectedOutput actualOutput
done' = not <$> done
notDone = not <$> done

clkDDR = tbClockGen @AsyncDDR (unsafeSynchronizer clkReal clkDDR done')
clkReal = tbClockGen @AsyncReal done'
clkDDR = tbClockGen @AsyncDDR (unsafeSynchronizer clkReal clkDDR notDone)
clkReal = tbClockGen @AsyncReal notDone
rstDDR = resetGen @AsyncDDR
rstReal = resetGen @AsyncReal

Expand All @@ -110,11 +110,11 @@ testBenchGS = done
expectedOutput = outputVerifier clkTest rstTest testoutputSync
actualOutput = ignoreFor clkReal rstReal enableGen d1 (dummy, dummy) (topEntityGS clkReal rstReal testInput)
done = expectedOutput actualOutput
done' = not <$> done
notDone = not <$> done

clkTest = tbClockGen @TB done'
clkDDR = tbClockGen @SyncDDR (unsafeSynchronizer clkTest clkDDR done')
clkReal = tbClockGen @SyncReal (unsafeSynchronizer clkTest clkReal done')
clkTest = tbClockGen @TB notDone
clkDDR = tbClockGen @SyncDDR (unsafeSynchronizer clkTest clkDDR notDone)
clkReal = tbClockGen @SyncReal (unsafeSynchronizer clkTest clkReal notDone)

rstTest = resetGen @TB
rstDDR = resetGen @SyncDDR
Expand All @@ -127,9 +127,9 @@ testBenchGA = done
expectedOutput = outputVerifier' clkReal rstReal testoutputAsync
actualOutput = ignoreFor clkReal rstReal enableGen d1 (dummy, dummy) (topEntityGA clkReal rstReal testInput)
done = expectedOutput actualOutput
done' = not <$> done
notDone = not <$> done

clkDDR = tbClockGen @AsyncDDR (unsafeSynchronizer clkReal clkDDR done')
clkReal = tbClockGen @AsyncReal done'
clkDDR = tbClockGen @AsyncDDR (unsafeSynchronizer clkReal clkDDR notDone)
clkReal = tbClockGen @AsyncReal notDone
rstDDR = resetGen @AsyncDDR
rstReal = resetGen @AsyncReal
28 changes: 14 additions & 14 deletions tests/shouldwork/DDR/DDRout.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -74,11 +74,11 @@ testBenchUS = done
actualOutput = ignoreFor clkDDR rstDDR enableGen d1 dummy (topEntityUS clkReal rstReal testInput)
expectedOutput = outputVerifier clkTest rstTest expected
done = expectedOutput actualOutput
done' = not <$> done
notDone = not <$> done

clkTest = tbClockGen @TB done'
clkDDR = tbClockGen @SyncDDR (unsafeSynchronizer clkTest clkDDR done')
clkReal = tbClockGen @SyncReal (unsafeSynchronizer clkTest clkReal done')
clkTest = tbClockGen @TB notDone
clkDDR = tbClockGen @SyncDDR (unsafeSynchronizer clkTest clkDDR notDone)
clkReal = tbClockGen @SyncReal (unsafeSynchronizer clkTest clkReal notDone)

rstTest = resetGen @TB
rstDDR = resetGen @SyncDDR
Expand All @@ -91,9 +91,9 @@ testBenchUA = done
actualOutput = ignoreFor clkDDR rstDDR enableGen d1 dummy (topEntityUA clkReal rstReal testInput)
expectedOutput = outputVerifier' clkDDR rstDDR expected
done = expectedOutput actualOutput
done' = not <$> done
clkDDR = tbClockGen @AsyncDDR done'
clkReal = tbClockGen @AsyncReal (unsafeSynchronizer clkDDR clkReal done')
notDone = not <$> done
clkDDR = tbClockGen @AsyncDDR notDone
clkReal = tbClockGen @AsyncReal (unsafeSynchronizer clkDDR clkReal notDone)
rstDDR = resetGen @AsyncDDR
rstReal = resetGen @AsyncReal

Expand All @@ -104,9 +104,9 @@ testBenchGA = done
actualOutput = ignoreFor clkDDR rstDDR enableGen d1 dummy (topEntityGA clkReal rstReal testInput)
expectedOutput = outputVerifier' clkDDR rstDDR expected
done = expectedOutput actualOutput
done' = not <$> done
clkDDR = tbClockGen @AsyncDDR done'
clkReal = tbClockGen @AsyncReal (unsafeSynchronizer clkDDR clkReal done')
notDone = not <$> done
clkDDR = tbClockGen @AsyncDDR notDone
clkReal = tbClockGen @AsyncReal (unsafeSynchronizer clkDDR clkReal notDone)
rstDDR = resetGen @AsyncDDR
rstReal = resetGen @AsyncReal

Expand All @@ -117,11 +117,11 @@ testBenchGS = done
actualOutput = ignoreFor clkDDR rstDDR enableGen d1 dummy (topEntityGS clkReal rstReal testInput)
expectedOutput = outputVerifier clkTest rstTest expected
done = expectedOutput actualOutput
done' = not <$> done
notDone = not <$> done

clkTest = tbClockGen @TB done'
clkDDR = tbClockGen @SyncDDR (unsafeSynchronizer clkTest clkDDR done')
clkReal = tbClockGen @SyncReal (unsafeSynchronizer clkTest clkReal done')
clkTest = tbClockGen @TB notDone
clkDDR = tbClockGen @SyncDDR (unsafeSynchronizer clkTest clkDDR notDone)
clkReal = tbClockGen @SyncReal (unsafeSynchronizer clkTest clkReal notDone)

rstTest = resetGen @TB
rstDDR = resetGen @SyncDDR
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2 changes: 1 addition & 1 deletion tests/shouldwork/Numbers/IntegralTB.hs
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Expand Up @@ -15,6 +15,6 @@ testBench = done
where
testInput = stimuliGenerator clk rst Integral.inputs
expectedOutput = outputVerifier' clk rst expected
done = expectedOutput (Integral.topEntity <$> testInput)
done = expectedOutput (topEntity <$> testInput)
clk = tbSystemClockGen (not <$> done)
rst = systemResetGen
8 changes: 4 additions & 4 deletions tests/shouldwork/Testbench/SyncTB.hs
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Expand Up @@ -53,9 +53,9 @@ testBench = done
expectedOutput = outputVerifier' clk9 rst9
(0 :> 1 :> $(listToVecTH ([2,3,4,6,7,8,9,11,12,13,15,16]::[Integer])))
done = expectedOutput (zeroAt0 clk9 rst9 (topEntity clk2 clk7 clk9 testInput))
done' = not <$> done
clk2 = tbClockGen @Dom2 (unsafeSynchronizer clk9 clk2 done')
clk7 = tbClockGen @Dom7 (unsafeSynchronizer clk9 clk7 done')
clk9 = tbClockGen @Dom9 done'
notDone = not <$> done
clk2 = tbClockGen @Dom2 (unsafeSynchronizer clk9 clk2 notDone)
clk7 = tbClockGen @Dom7 (unsafeSynchronizer clk9 clk7 notDone)
clk9 = tbClockGen @Dom9 notDone
rst7 = resetGen @Dom7
rst9 = resetGen @Dom9

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