WIP: Windows 11 support

OSXSAVE feature support in the root OS
chp-io · Oct 9, 2024 · d0fa99a · d0fa99a
1 parent 98b82a9
commit d0fa99a
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Showing 2 changed files with 13 additions and 1 deletion.
diff --git a/deps/hypervisor/bfvmm/src/hve/arch/intel_x64/vcpu.cpp b/deps/hypervisor/bfvmm/src/hve/arch/intel_x64/vcpu.cpp
@@ -102,6 +102,10 @@ setup()
 
     if (feature_information::ecx::xsave::is_enabled()) {
         g_cr4_reg |= ::intel_x64::cr4::osxsave::mask;
+        bfalert_info(0, "--> vcpu::setup::osxsave on");
+    }
+    else {
+        bfalert_info(0, "--> vcpu::setup::osxsave off");
     }
 
     if (extended_feature_flags::subleaf0::ebx::smep::is_enabled()) {
@@ -552,6 +556,7 @@ vcpu::dump(const char *str)
 void
 vcpu::halt(const std::string &str)
 {
+    bfalert_info(0, "--> bareflank halt");
     this->dump(("halting vcpu: " + str).c_str());
     ::x64::pm::stop();
 }
@@ -1452,7 +1457,7 @@ void
 vcpu::set_cr4(uint64_t val) noexcept
 {
     vmcs_n::cr4_read_shadow::set(val);
-    vmcs_n::guest_cr4::set(val | m_global_state->ia32_vmx_cr4_fixed0);
+    vmcs_n::guest_cr4::set(val | m_global_state->ia32_vmx_cr4_fixed0 | ::intel_x64::cr4::osxsave::mask);
 }
 
 uint64_t

diff --git a/deps/hypervisor/bfvmm/src/hve/arch/intel_x64/vmexit/control_register.cpp b/deps/hypervisor/bfvmm/src/hve/arch/intel_x64/vmexit/control_register.cpp
@@ -253,6 +253,8 @@ control_register_handler::control_register_handler(
 {
     using namespace vmcs_n;
 
+    bfalert_info(0, "--> control_register_handler");
+
     vcpu->add_handler(
         exit_reason::basic_exit_reason::control_register_accesses,
     {&control_register_handler::handle, this}
@@ -333,6 +335,9 @@ control_register_handler::enable_wrcr4_exiting(
     vmcs_n::value_type mask)
 {
     mask |= m_vcpu->global_state()->ia32_vmx_cr4_fixed0;
+    mask |= ::intel_x64::cr4::osxsave::mask;
+
+    bfalert_nhex(0, " control_register_handler::enable_wrcr4_exiting::mask ", mask);
     vmcs_n::cr4_guest_host_mask::set(mask);
 }
 
@@ -385,6 +390,8 @@ control_register_handler::execute_wrcr4(
     emulate_rdgpr(vcpu);
     vcpu->set_gr2(vcpu->cr4());
     vcpu->set_cr4(vcpu->gr1());
+    bfalert_nhex(0, "--> mov_to_cr -> execute_wrcr4 old ", vcpu->gr2());
+    bfalert_nhex(0, "--> mov_to_cr -> execute_wrcr4 new ", vcpu->cr4());
 }
 
 // -----------------------------------------------------------------------------