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Build(deps): Bump third_party/ibex from 87dfd07 to 8f4c75c #6107

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Build(deps): Bump third_party/ibex from 87dfd07 to 8f4c75c

Build(deps): Bump third_party/ibex from 87dfd07 to 8f4c75c #6107

Triggered via pull request December 23, 2024 07:32
@dependabotdependabot[bot]
opened #2715
dependabot/submodules/third_party/ibex-8f4c75c
Status Failure
Total duration 1h 6m 15s
Artifacts 47

main.yml

on: pull_request
Matrix: build-binaries
Build tools
10m 42s
Build tools
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 24s
Style check
Verify README Correctness (Installation From Sources)
42m 7s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
2m 43s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
5m 22s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
31m 2s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
57m 0s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 23s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
17m 1s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
45m 30s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
41m 26s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 22s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
1m 41s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 23s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

2 errors and 4 warnings
Large Designs Tests / Ibex (Vivado synthesis)
Process completed with exit code 2.
Large Designs Tests / Ibex (F4PGA synthesis)
Process completed with exit code 2.
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
292 MB
binaries-package
23.2 MB
binaries-plugin
41.7 MB
binaries-pysynlig
651 MB
binaries-release
42 MB
bp_e_bp_unicore_cfg.edif
3.92 MB
bsg-logs
5.57 MB
bsg-outputs
1.73 MB
formal-verification-logs-simple
18.5 MB
formal-verification-logs-sv2v
62.8 MB
formal-verification-logs-yosys
50.4 MB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
4.58 MB
opentitan-logs-quick
827 KB
plots_binaries-asan
48.6 KB
plots_binaries-package
30.2 KB
plots_binaries-plugin
30.9 KB
plots_binaries-pysynlig
61.9 KB
plots_binaries-release
29.8 KB
plots_blackparrot_synth_asic
257 KB
plots_blackparrot_synth_xilinx
109 KB
plots_blackparrot_synth_xilinx_python
238 KB
plots_build_tools
80.2 KB
plots_formal_verification_simple
115 KB
plots_formal_verification_sv2v
118 KB
plots_formal_verification_yosys
97.4 KB
plots_ibex_synth
20 KB
plots_ibex_synth_f4pga
41.4 KB
plots_opentitan_9d82960888_synth
176 KB
plots_opentitan_parse_report_full
82.5 KB
plots_opentitan_parse_report_quick
38.2 KB
plots_opentitan_synth
311 KB
plots_tests_asan_read_systemverilog
223 KB
plots_tests_asan_read_uhdm
166 KB
plots_tests_plugin_read_systemverilog
36.3 KB
plots_tests_plugin_read_uhdm
33.7 KB
plots_tests_release_read_systemverilog
34.9 KB
plots_tests_release_read_uhdm
33 KB
plots_veer_synth
38.4 KB
python_bp_e_bp_unicore_cfg.edif
3.92 MB
results_parsing_tests_asan_read_systemverilog Expired
1.6 MB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
1.53 MB
results_parsing_tests_plugin_read_uhdm Expired
1.78 MB
results_parsing_tests_release_read_systemverilog Expired
1.48 MB
results_parsing_tests_release_read_uhdm Expired
1.73 MB
tools
39.2 MB