Chisel v7.0.0-M2

Features

• Add getClassType API to Definition[T <: Class]. (by @mikeurbach in #3877)
  This allows users to get a ClassType for use in other Property types, which is especially useful when constructing aggregate Property types of a specific Class.
• Add suggestName method to HasTarget (by @debs-sifive in #3881)
  HasTarget trait now also exposes suggestName method of a NamedComponent.
• Print the optional Printable passed to stop ops (by @nandor in #3886)
  The message passed to stop is no longer ignored. The construct was extended to accept Printable.
• Add DeletedPath for targets that no longer exist. (by @mikeurbach in #3937)
  Sometimes a generator wants to emit a Path that targets some Data, but that Data isn't always produced by the generator. The DeletedPath can be used to represent the presence of a Path, but the absence of a Data in this case.
• Make firtool options for elaborateGeneratedModule in workspace parametric (by @rameloni in #3952)
  This adds the support in Chiselsim to configure the workspace with additional args for firtool (#3932). The user can specify how the sv circuit is compiled for simulation (i.e. including debug information -g).
• Add a new BoringUtils.drive API for boring to drive a sink. (by @mikeurbach in #3960)
  This API allows users to bore to a sink they plan to drive, which complements the existing API to bore from a source to read.
• Add requireIsAnnotatable for better errors when annotating literals (by @jackkoenig in #3968)
  This gives much better error messages when accidentally dontTouching a literal
• Add extension points on Data for customizing Connectable behavior. (by @mikeurbach in #3978)
  The user can override these methods to customize how their Data applies waive, squeeze, and exclude in its Connectable.
• Add support for generic intrinsic expressions and statements. (by @dtzSiFive in #3986)
  Intrinsic expressions and statements are now supported, streamlining their use. These should be preferred over intrinsicModule's, which in the future will be deprecated and removed.
• make SerializableModuleGenerator work with D/I (by @sequencer in #4003)
• Add Instanitate.definition to get Definition from cache. (by @sequencer in #4020)
• Add private Module API and internal DataMirror API for moduleIOs. (by @mikeurbach in #4036)
  The DataMirror API allows users who know what they're doing to access a module's ports before it is closed.
• [LTL] Added overloadings for AssertProperty (by @dobios in #4037)
• [Formal] Expose Btor2 target (by @dobios in #4035)
  • [Formal] Allow for Chisel to be compiled to btor2 for Bounded Model Checking using ChiselStage.emitBtor2.
• Add modulePorts and fullModulePorts in DataMirror for Instance (by @debs-sifive in #4076)
  Added modulePorts and fullModulePorts methods in DataMirror that returns all ports on an Instance of a module.
• Add .toRelativeTargetToHierarchy (by @mwachs5 in #4067)
  Add .toRelativeTargetToHierarchy for getting .toRelativeTarget functionality when the root is a Definition or Instance.
• Don't ... top of stack trace if it isn't actually trimmed (by @jackkoenig in #4142)
• [LTL] Add support for new sequence and property ops (by @dobios in #4120)
  • [LTL] Add support for intersect, repeat, gotoRepeat, and nonConsecutiveRepeat ops.
• PeekPokeAPI: include source location on failed expect() calls. (by @kivikakk in #4144)
  SimulationData.expect calls now record source location and report it in the FailedExpectationException on failure.
• Preserve literals across .asUInt (by @jackkoenig in #4148)
  This is mostly useful for initial values for async reset registers and for constructing literal values in testing contexts (e.g. ChiselSim). It also should slightly reduce memory use and .fir size.
• Preserve literal value across .asSInt and .zext (by @jackkoenig in #4151)
• Preserve UInt and SInt literals across .pad (by @jackkoenig in #4156)
• Add support for marking things as readOnly (by @jackkoenig in #4190)
  Users can call .readOnly on any Data to prevent connections to the returned value. Resolves #1267.
• Add ChiselStage.emitCHIRRTLFile (by @jackkoenig in #4232)
  Emits a file without returning the serialized object which is more memory efficient and supports > 2 GiB of serialized FIRRTL text.
• Make requireTypeEquivalent public and add context message (by @mwachs5 in #4243)
  Make Add a contextual message to Data.requireTypeEquivalent and expose a public API in DataMirror.requireTypeEquivalent, to make it easier for user code to have good error messages when requiring type equivalence between two chisel Datas
• Add map method for Valid (by @tymcauley in #4255)
  Users can now apply a function f to the bits field of a Valid instance with the new Valid.map(f) method.
• Add more information when probe types don't match (by @mwachs5 in #4269)
  Add more information to the error message when attempting to probe.define to a mismatched chisel type.

API Modification

• Fix tests to avoid inferred width ports on public modules. (by @dtzSiFive in #3869)
  Main module are "public" (#3813, soon mandatory) which means they cannot have inferred widths or abstract resets. Code relying on old behavior will presently encounter an error in firtool.
• Remove circt.Intrinsic annotation. (by @dtzSiFive in #3945)
  IntrinsicModules (intmodule's in FIRRTL) have replaced this entirely for some time now.
• [svsim] Expose further verilator options for trace file name and simulation speed optimization (by @kammoh in #3985)
• Make AssertPropertyLike.createIntrinsic protected (by @jackkoenig in #4058)
  It should never have been a public API
• checkTypeEquivalence now considers ProbeInfo (by @mwachs5 in #4064)
  Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).
• Make "deprecated public" binding APIs private (by @jackkoenig in #4177)
  These chisel3.internal APIs should never have been public in the first place.
• Fix width of ChiselEnum values in emitted FIRRTL (by @jackkoenig in #4200)
  Fixes #4159.
  Previously, the width reported by Chisel under .getWidth was inconsistent with the width of the emitted FIRRTL for ChiselEnum values cast to UInt.
  Temporarily preserve the old behavior under CLI option --use-legacy-width (formerly known as --use-legacy-shift-right-width). Users are encouraged to build Verilog with and without this option enabled and diff the result to verify that this change in width behavior did not silently affect the correctness of their designs.
• Preserve literals across .asTypeOf (by @jackkoenig in #4168)
  Casting a literal (of any type) to another type with .asTypeOf will result in a literal of the new type. For non-literals, the FIRRTL representation will now be a little bit more efficient.
• Intern Width (by @jackkoenig in #4242)
  • UnknownWidth becomes a case object (Drop () when using it).
  • KnownWidths 0-1024 are interned
• SourceInfo: simplify the common case for makeMessage, print it differently (by @mwachs5 in #4249)
  Add a default to SourceInfo.makeMessage() so that users don't always have to write makeMessage(x => x). Change the toString of SourceLine so that it puts a colon instead of a space between the file name and line number, which makes it possible to click-to-source in editors like VSCode.
• Micro-optimize Direction (by @jackkoenig in #4251)
  • Specified and actual direction information are each now stored as single bytes rather than references.
  • This reduces the memory use of a typical bound UInt from 72 bytes shallow, 128 bytes retained to 64 bytes shallow, 120 bytes retained.
  • The change is mostly source compatible, but ActualDirection.Bidirectional, has changed slightly to memoize its two possibilities (Bidirectional.Default and Bidirectional.Flipped). There are deprecations for the typical APIs

API Deprecation

• IntrinsicModule: deprecate in favor of intrinsic expressions. (by @dtzSiFive in #4060)
  IntrinsicModule has been replaced by Intrinsic and IntrinsicExpr .
• Make it a warning to have too-wide literal values in Bundle Literals (by @jackkoenig in #4093)
• Mark return value of .asTypeOf as "deprecated read-only" (by @jackkoenig in #4198)
  Previously, .asTypeOf would return a Wire. To get the old behavior, wrap the .asTypeOf call in WireInit(...).
• [LTL] Deprecate disable intrinsic (by @dobios in #4237)

Backend Code Generation

• Assume: Use plain FIRRTL assume + format string instead of printf + assume. (by @dtzSiFive in #3878)
  chisel3.Assume now directly emits a FIRRTL assume with the specified format message.
  Previously a when not(predicate): printf(...) was emitted followed by a message-less assume.
  The resulting SystemVerilog will change, more aligned with assert output but specifically uses $error(..) instead of a printf guarded by the usual printf guards.
• Add ifElseFatal intrinsics; use it for chisel3.assert emission (by @uenoku in #3825)
  Support circt_chisel_ifelsefatal intrinsics and use it for chisel3.assert emission.
• Add a label "chisel3_builtin" to ifElseFatal intrinsic (by @uenoku in #3912)
  Add a label "chisel3_builtin" to ifElseFatal intrinsic.
• Revert move to intrinsic for assert due to performance impact (by @dtzSiFive in #3916)
  Revert recent change moving to intrinsic due to poor performance/scaling with many many intmodule's.
• Make SRAMs directly emit FIRRTL memories (by @debs-sifive in #3955)
  SRAMs updated to directly emit FIRRTL memories (as opposed to creating SyncReadMems.
• Use intrinsic expressions for most intrinsics (by @dtzSiFive in #4000)
  Change intrinsic wrappers to use intrinsic expressions instead of intrinsic modules.
  PlusArgsTest(x, str) is now deprecated as first argument is unused. Use PlusArgsTest(str).
• HasBeenReset: use intrinsic expression (by @dtzSiFive in #4011)
• Add ifElseFatal intrinsics; use it for chisel3.assert emission (by @dtzSiFive in #4001)
  Support circt_chisel_ifelsefatal intrinsics and use it for chisel3.assert emission.
• [LTL] Port LTL intrinsics to use IntrinsicExpr instead of IntrinsicModule (by @dobios in #4053)
  • [LTL] Port LTL intrinsics to use IntrinsicExpr instead of IntrinsicModule
• [LTL] Plumb sourceInfo so source locations are in user-code. (by @dtzSiFive in #4057)
  LTL properties and related now use source information from user code.
• Remove line contents from assertion messages (by @jackkoenig in #4078)
  Also remove line and column when a message is provided.

Performance

• Optimize BitPat factory from UInt literals (by @jackkoenig in #3988)
  Speeds up conversion of UInt literals to BitPat by ~9x in practice, ~70x for large UInts.
• Optimize truth table merge (by @jackkoenig in #3993)
• make TruthTable in DecodeTable lazy (by @sequencer in #4178)
  make TruthTable in DecodeTable lazy to speed up decoding.
• Share ChildBinding objects between siblings (by @jackkoenig in #4238)
  This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
• Remove autoSeedVar, use Boolean to distinguish suggested or autoSeed (by @jackkoenig in #4252)
  • Combined with #4251, reduces the memory use of a typical bound UInt from 64 bytes shallow, 120 bytes retained, to 56 bytes shallow, 112 bytes retained.
• Move circuitVar from HasId to BaseModule (by @jackkoenig in #4253)
  • This removes a 4-byte field (8-bytes with heap > 32 GB) from all Data
• Optimize Record._elements to not duplicate VectorMap if possible (by @jackkoenig in #4254)
  This reduces memory use of a typical bundle by 20%.
• Share Node objects between siblings (by @jackkoenig in #4259)
  This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
• Optimize .readOnly to only create views when necessary (by @jackkoenig in #4271)
• Specialize Index for literal indices with LitIndex (by @jackkoenig in #4268)
  This saves 16-bytes per Vec element.

Fixes

• Get ChiselSim working with CIRCT 1.66+ (by @seldridge in #3890)
• Fix ChiselStage and Builder handling of logging (by @jackkoenig in #3895)
  • Adds support for --log-level to circt.stage.ChiselStage
  • Previously, object circt.stage.ChiselStage was ignoring the Logger.
  • Also, Chisel was not creating its own logger scope which could lead to clobbering of the Console when running invoking Chisel in the same process multiple times.
• Make logger annotations unserializable (by @seldridge in #3901)
• Support serializing large (> 2 GiB) annotation files (by @jackkoenig in #3905)
• Allow BoringUtils.bore to work on probes (by @seldridge in #3908)
• toBigInt should round identically for Double and BigDecimal (by @mvanbeirendonck in #3921)
• Fix Data.findFirstTypeMismatch to check all elements of Bundles (by @jackkoenig in #3928)
  Fixes DataMirror.checkTypeEquivalence to actually check all fields of Bundles and Records. This may expose latent bugs in user code.
• Fix incorrect width for negative SInt literals (by @SpriteOvO in #3943)
• Support literals in DataView (by @jackkoenig in #3964)
  View of literals will now themselves be literals. This also fixes an internal bug related to views of literals.
• Fix === for abstract Reset types (by @jackkoenig in #3979)
  Previously, the function would infinitely recurse resulting in a stack overflow.
• Add layers for colored probe types or enablelayer (by @seldridge in #3984)
• In BoringUtils.drive, don't bore into the final module for inputs. (by @mikeurbach in #3998)
  This follows up on #3960 to address the behavior at the final module for the sink being driven. We already have special handling for boring out from the original source, and we need the inverse here. When we reach the final sink, if it is an input port, we should use it, rather than boring into the module and connecting to it.
• Provide require message for negative widths (by @jackkoenig in #4008)
  Fixes #4007
• Fix Nested Instantiate (by @sequencer in #4018)
  Fix Nested Instantiate
• Fix Typo in ExtractFromVecSizeZero warning message (by @jerryz123 in #4029)
• [LTL] Fix verif_* -- these are statements not expressions, no ret value. (by @dtzSiFive in #4061)
  Fix LTL verif statements.
• Add support for Vec literals of empty Vecs (by @jackkoenig in #4070)
• Fix literal handling for views of empty Aggregates (by @jackkoenig in #4071)
  Previously, a view of an empty aggregate would incorrectly always have a litValue of 0.
• Materialize wires for .ref of Aggregate views (by @jackkoenig in #4080)
  Fix muxing and probing of views of Aggregates
• [SVSim] Fixed non-firing AssertProperty in SVSim (by @dobios in #4087)
  • [SVSim] Fixed AssertProperty failing to fire in verilator simulation.
• Fix widths for literal values in Bundle literals (by @jackkoenig in #4082)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
• BoringUtils: Fix tapAndRead to return same type even when not boring. (by @dtzSiFive in #4084)
  Always return fully aligned result from tapAndRead, even if no boring performed.
• Fix boring tap of non-passive source from parent. (by @dtzSiFive in #4083)
  Fix tapping mix-alignment signal from parent.
• Don't warn when 0.U used as value for 0-bit BundleLit field (by @jackkoenig in #4097)
• Fix 0 width signals chiselsim (by @rameloni in #4100)
  Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.
• Support views of ports in ChiselSim (by @jackkoenig in #4107)
  Also fix reifySingleData to return the Data itself if it is not a view.
• FixedIO__Modules with various kinds of probe ports (by @mwachs5 in #4105)
  Fix for #4102. Now supported are FlatIO (and therefore FixedIO___Module) of:
  • Probe(Element)
  • Probe(Aggregate)
  • Aggregate(Probes)
  • Aggregates containing any of the above
• Fix svsim with gcc14 (by @Emin017 in #4121)
• Suppress exception throwing in Data.toString (by @jackkoenig in #4147)
  This makes .toString behavior better outside of Chisel elaboration contexts.
• Error when calling define targeting a child of a probe (by @jackkoenig in #4175)
  This is already an error caught in firtool, now Chisel will error earlier.
• Support XMRs to Analog in D/I (by @jackkoenig in #4181)
• Distinguish identity views from single-target views (by @jackkoenig in #4186)
  Fixes #4185, Fixes #4187
• Initialize scala.util.control.NonFatal in Builder (by @jackkoenig in #4195)
• Fix BoringUtils for identity views (by @jackkoenig in #4220)
• make FixedIOBaseModule.io public (by @sequencer in #4216)
  make FixedIOModule work with D/I
• Name the targets of identity views (by @jackkoenig in #4222)
• Make isView safe outside of Builder context (by @jackkoenig in #4228)
• Emit FIRRTL bulk connects even for "input" wires (by @jackkoenig in #4219)
• Use :<>= in VecInit methods instead of := or <> (by @jackkoenig in #4248)
  Previously, VecInit would try to "intelligently" select := or <> depending on if the type is bidirectional. :<>= has the desirable behavior here for both passive and bidirectional types. It also has the advantage over <> of handling internal wires.
• Fix .toString for dynamic indexing (by @jackkoenig in #4260)

Documentation

• [docs] Improve firtool versioning table (by @jackkoenig in #3858)
• [website] Update chisel-template repo link to chipsalliance (by @jackkoenig in #3871)
• [docs] Add initial ChiselTest migration doc (by @jackkoenig in #3870)
• [docs] Fix ChiselTest migration doc (by @jackkoenig in #3875)
• Add explanation for Class and Object, with examples. (by @mikeurbach in #3880)
• [docs] Update links to point to chipsalliance/chisel-template (by @jackkoenig in #3872)
• Rename Scala CLI template to example (by @jackkoenig in #3917)
  Existing links to https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
• [website] Bump Docusaurus to 3.1.1 and fix broken anchors (by @jackkoenig in #3948)
• Removed FixedPoint reference in muxes-and-input-selection.md (by @jackkoenig in #3956)
• Add Tywaves project to community projects page (by @rameloni in #4013)
• Add a test for issue 4159 (by @jackkoenig in #4161)
• Add more exhaustive tests for .asTypeOf (by @jackkoenig in #4160)
• Fix import path in docstring (by @tymcauley in #4256)

Dependency Updates

• Use c++14 to pass the verilator check (by @Emin017 in #3876)
  Change ChiselSim to requires a C++14 compiler.
• [cd] Bump CIRCT from firtool-1.66.0 to firtool-1.67.0 (by @chiselbot in #3903)
• [cd] Bump CIRCT from firtool-1.67.0 to firtool-1.68.0 (by @chiselbot in #3931)
• [cd] Bump CIRCT from firtool-1.68.0 to firtool-1.69.0 (by @chiselbot in #3941)
• [cd] Bump CIRCT from firtool-1.69.0 to firtool-1.71.0 (by @chiselbot in #3950)
• [cd] Bump CIRCT from firtool-1.71.0 to firtool-1.72.0 (by @chiselbot in #3969)
• [cd] Bump CIRCT from firtool-1.72.0 to firtool-1.73.0 (by @chiselbot in #4002)
• [cd] Bump CIRCT from firtool-1.73.0 to firtool-1.74.0 (by @chiselbot in #4038)
• Add Scala 2.13.14 to cross-build (by @jackkoenig in #4044)
• Bump to Scala 2.13.14 (by @jackkoenig in #4049)
• Bump dependencies and delete moultingyaml (by @jackkoenig in #4063)
  • scalatest: 3.2.14 => 3.2.18
  • scalacheck-1-16:3.2.14.0 => scalacheck-1-18:3.2.18.0
  • json4s-native: 4.0.6 => 4.0.7
  • commons-text: 1.10.0 => 1.12.0
  • os-lib: 0.9.1 => 0.10.0
  • upickle: 3.1.0 => 3.3.0
  • Delete moultingyaml, it has been unused for a long time
  • Make Mill versions consistent with SBT versions
• [cd] Bump CIRCT from firtool-1.74.0 to firtool-1.75.0 (by @chiselbot in #4069)
• [cd] Bump CIRCT from firtool-1.75.0 to firtool-1.76.0 (by @chiselbot in #4146)
• [cd] Bump CIRCT from firtool-1.76.0 to firtool-1.77.0 (by @chiselbot in #4277)

Build and Internal Changes

• [ci] Update jextract download URL (by @SpriteOvO in #3868)
• [binder] Specify the new attribute layers for firrtl.instance (by @SpriteOvO in #3902)
• [binder] Add OM example as a test case (by @SpriteOvO in #3904)
• remove outdated jextract in nix overlay (by @OceanS2000 in #3924)
• Some fixes related to OM (by @SpriteOvO in #3940)
• Fix integration test for PanamaProperty (by @OceanS2000 in #3935)
• Add PORT option to make serve in website/ subdir. (by @mmaloney-sf in #3947)
• Recognize OM evaluator reference value (by @SpriteOvO in #3946)
• Specify desiredName as defname for extmodule, specify right convention for modules (by @SpriteOvO in #3958)
• Add reference benchmarking flow (by @jackkoenig in #3987)
• Check format with mill (by @sequencer in #3992)
• Add integration test for PanamaCIRCT to firrtl converter (by @OceanS2000 in #3936)
• [ci] Stop copying body over to backports in backport-fixup (by @jackkoenig in #4005)
• bump nix circt to 1.72 (by @sequencer in #4006)
• Subdivide OM primitive values into Scala types (by @SpriteOvO in #4028)
• [LTL] Send generated FIRRTL through to SV to ensure this works. (by @dtzSiFive in #4062)
• Remove input probes in tests (by @dtzSiFive in #4065)
• add test for FlatIO port ordering (by @mwachs5 in #4113)
  Added a unit test for FlatIO Ordering being maintained
• Bump versions of Github actions to versions using Node 20 (by @jackkoenig in #4116)
• Add and use Mill wrapper script (by @jackkoenig in #4119)
• Update sbt-buildinfo to 0.12.0 (by @scala-steward in #4131)
• Merge two conditional due to same body (by @colin4124 in #4192)
• Update mill-main to 0.11.8 (by @scala-steward in #4210)
• Update scalatest to 3.2.19 (by @scala-steward in #4211)
• Update scalacheck-1-18 to 3.2.19.0 (by @scala-steward in #4212)

Full Changelog: v7.0.0-M1...v7.0.0-M2