Chisel v5.3.0

Fixes

• Fix Nested Instantiate (backport #4018) (by @mergify[bot] in #4026)
  Fix Nested Instantiate
• Add support for Vec literals of empty Vecs (backport #4070) (by @mergify[bot] in #4072)
• Fix literal handling for views of empty Aggregates (backport #4071) (by @mergify[bot] in #4074)
  Previously, a view of an empty aggregate would incorrectly always have a litValue of 0.
• [SVSim] Fixed non-firing AssertProperty in SVSim (backport #4087) (by @mergify[bot] in #4088)
  • [SVSim] Fixed AssertProperty failing to fire in verilator simulation.
• Materialize wires for .ref of Aggregate views (backport #4080) (by @mergify[bot] in #4085)
  Fix muxing and probing of views of Aggregates
• Fix widths for literal values in Bundle literals (backport #4082) (by @mergify[bot] in #4091)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
• Fix 0 width signals chiselsim (backport #4100) (by @mergify[bot] in #4103)
  Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.
• Fix svsim with gcc14 (backport #4121) (by @mergify[bot] in #4122)

Dependency Updates

• Add Scala 2.13.14 to cross-build (backport #4044) (by @mergify[bot] in #4046)
• Add 2.12.19 to cross-build (by @jackkoenig in #4050)

Build and Internal Changes

• [5.x] Enable MiMa for v5.2.0 (by @chiselbot in #4016)
• [ci] Stop copying body over to backports in backport-fixup (backport #4005) (by @mergify[bot] in #4042)
• add test for FlatIO port ordering (backport #4113) (by @mergify[bot] in #4114)
  Added a unit test for FlatIO Ordering being maintained
• Bump versions of Github actions to versions using Node 20 (backport #4116) (by @mergify[bot] in #4117)
• Add and use Mill wrapper script (backport #4119) (by @mergify[bot] in #4124)

Full Changelog: v5.2.0...v5.3.0