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[docs] Add Cookbook entry for Verilog case equality (IsX) #4605

Merged
merged 4 commits into from
Jan 9, 2025
Merged

[docs] Add Cookbook entry for Verilog case equality (IsX) #4605

merged 4 commits into from
Jan 9, 2025

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jackkoenig
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Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you add appropriate documentation in docs/src?
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  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • Documentation or website-related

Desired Merge Strategy

  • Squash

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  • Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
  • Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
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  • Did you do one of the following when ready to merge:
    • Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
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@jackkoenig jackkoenig added the Documentation Only changing documentation label Jan 9, 2025
mwachs5
mwachs5 reviewed Jan 9, 2025
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docs/src/cookbooks/cookbook.md Outdated
class XSafeAssert extends Module {
val in = IO(Input(UInt(8.W)))

// Assert that in is never zero, but also guard against X
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Suggested change
// Assert that in is never zero, but also guard against X
// Assert that `in` is never zero, but also allow X

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I phrased it differently, what do you think?

@jackkoenig jackkoenig enabled auto-merge (squash) January 9, 2025 18:38
@jackkoenig jackkoenig merged commit 5d68bea into main Jan 9, 2025
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@jackkoenig jackkoenig deleted the isx-doc branch January 9, 2025 19:04
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@tymcauley tymcauley tymcauley left review comments

@mwachs5 mwachs5 mwachs5 approved these changes

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@jackkoenig @tymcauley @mwachs5