fix up extra waveform dump behavior in svsim (backport #4592)

[mergify]

When added require statement in ChiselSim/svsim, the delay value will be set to 0, which will cause an extra dump waveform behavior. So we only call eval_step once to update the design model.

This will fix #4516.

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you add appropriate documentation in docs/src?
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• Did you add text to be included in the Release Notes for this change?

Type of Improvement

• Bugfix

Desired Merge Strategy

• Squash: The PR will be squashed and merged (choose this if you have no preference).

Release Notes

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
• Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
• Did you review?
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• Did you do one of the following when ready to merge:
  • Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
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This is an automatic backport of pull request #4592 done by [Mergify](https://mergify.com).