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[ChiselSim] Add Inline Layer Control #4555

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merged 5 commits into from
Dec 11, 2024

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Add support for ChiselSim to turn on inline layers. This requires a different approach than how this worked for extract layers in order to continue to support the ability to "enable all" layers. For extract layers, this was straightforward: all files which looked like layer files could be included. However, for inline layers, to enable all layers requires knowledge of the layers that exist because Verilog preprocessor defines must be hand-crafted.

The first part of this patch adds support for layer ABIs. After that, the DesignAnnotation is widened to include information about what layers were elaborated. Finally, ChiselSim and svsim classes/functions are untangled to make it possible to add information to the compiler options after elaborating the circuit.

There are stubs in here to add support for extract layers to work the same way. I'd like to land this patch first and then clean that up following.

Commits should be reviewed individually.

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Fix ChiselSim so that inline layers can be enabled using the existing layerControl argument to simulators.

@seldridge seldridge requested a review from jackkoenig December 10, 2024 04:22
@seldridge seldridge changed the title Dev/seldridge/chiselsim inline layers [ChiselSim] Add Inline Layer Control Dec 10, 2024
@seldridge seldridge requested review from rwy7 and dtzSiFive December 10, 2024 04:22
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This also should be updated to work with ChiselRunners.runTester.

@seldridge seldridge marked this pull request as draft December 10, 2024 17:28
@seldridge seldridge force-pushed the dev/seldridge/chiselsim-inline-layers branch from caf364b to 362d104 Compare December 10, 2024 20:59
@seldridge seldridge marked this pull request as ready for review December 10, 2024 21:07
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Generally LGTM, a few nits and a question/point about whether certain APIs should be public or private.

core/src/main/scala/chisel3/Layer.scala Outdated Show resolved Hide resolved
core/src/main/scala/chisel3/internal/Builder.scala Outdated Show resolved Hide resolved
src/main/scala-2/chisel3/simulator/LayerControl.scala Outdated Show resolved Hide resolved
Add a function that returns that sequence of all layers from the current
layer up to the root.  This is part of forthcoming support for different
layer convention ABIs which need to use this information in their ABI
utility functions.

Signed-off-by: Schuyler Eldridge <[email protected]>
Add an enumeration and functions that can be used to help generate the
information for the two standard layer convention ABIs.

Signed-off-by: Schuyler Eldridge <[email protected]>
Add a field to the `DesignAnnotation` that stores all layers that were
generated in a run of Chisel.  This is intended to be used by testing APIs
that need to know what layers exist in order to turn them all on or to
error if a user tries to enable a layer that does not exist.

Signed-off-by: Schuyler Eldridge <[email protected]>
Add a member function `preprocessorDefines` to `LayerControl.Type` which
will return any preprocessor defines that should be set to enable the
requested layers.

Add an abstract member function, `getLayerSubset`, which layer control
concrete types implement to make the preprocessor define function work.

Signed-off-by: Schuyler Eldridge <[email protected]>
Extend ChiselSim with the ability to control inline layers.  This requires
untangling some of the way that compilation settings are passed into a
`Simulator` because these options need to be added to after Chisel
elaboration.  E.g., to enable all inline layers, this requires knowing all
the layers that were created.  This didn't come up previously with extract
layers as all layer files could be blindly included for this case.

In susbequent commits, I will cleanup the way that extract layers work to
use the same code that is introduced here.

Signed-off-by: Schuyler Eldridge <[email protected]>
@seldridge seldridge force-pushed the dev/seldridge/chiselsim-inline-layers branch from c61fb86 to bc063c0 Compare December 11, 2024 04:13
@seldridge seldridge merged commit bc063c0 into main Dec 11, 2024
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@seldridge seldridge deleted the dev/seldridge/chiselsim-inline-layers branch December 11, 2024 04:37
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2 participants