Deploying to gh-pages from @ 1b64e06 🚀

chisel3/docs/appendix/experimental-features.html

@@ -56,7 +56,7 @@ <h3 id="bundle-literals-">Bundle Literals <a name="bundle-literals"></a></h3>
 <span class="o">}</span>
 </code></pre></div></div>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">Example</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">output</span> <span class="p">[</span><span class="mi">7</span><span class="o">:</span><span class="mi">0</span><span class="p">]</span> <span class="n">out_a</span><span class="p">,</span>	<span class="c1">// experimental-features.md:21:15</span>
   <span class="kt">output</span>       <span class="n">out_b</span>	<span class="c1">// experimental-features.md:21:15</span>
@@ -79,7 +79,7 @@ <h3 id="bundle-literals-">Bundle Literals <a name="bundle-literals"></a></h3>
 <span class="o">}</span>
 </code></pre></div></div>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">Example2</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">output</span> <span class="p">[</span><span class="mi">7</span><span class="o">:</span><span class="mi">0</span><span class="p">]</span> <span class="n">out_a</span><span class="p">,</span>	<span class="c1">// experimental-features.md:36:15</span>
   <span class="kt">output</span>       <span class="n">out_b</span>	<span class="c1">// experimental-features.md:36:15</span>
@@ -108,7 +108,7 @@ <h3 id="bundle-literals-">Bundle Literals <a name="bundle-literals"></a></h3>
 <span class="o">}</span>
 </code></pre></div></div>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">Example3</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">output</span> <span class="p">[</span><span class="mi">7</span><span class="o">:</span><span class="mi">0</span><span class="p">]</span> <span class="n">out_a</span><span class="p">,</span>	<span class="c1">// experimental-features.md:62:15</span>
                <span class="n">out_b_foo</span>	<span class="c1">// experimental-features.md:62:15</span>
@@ -133,7 +133,7 @@ <h3 id="vec-literals">Vec Literals</h3>
   <span class="n">out</span> <span class="o">:=</span> <span class="nv">Vec</span><span class="o">.</span><span class="py">Lit</span><span class="o">(</span><span class="mh">0xa</span><span class="o">.</span><span class="py">U</span><span class="o">,</span> <span class="mh">0xbb</span><span class="o">.</span><span class="py">U</span><span class="o">)</span>
 <span class="o">}</span>
 </code></pre></div></div>
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">VecExample1</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -158,7 +158,7 @@ <h3 id="vec-literals">Vec Literals</h3>
 <span class="o">}</span>
 </code></pre></div></div>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">VecExample1a</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -184,7 +184,7 @@ <h3 id="vec-literals">Vec Literals</h3>
 <span class="o">}</span>
 </code></pre></div></div>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">VecExample2</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">output</span> <span class="p">[</span><span class="mi">3</span><span class="o">:</span><span class="mi">0</span><span class="p">]</span> <span class="n">out_0</span><span class="p">,</span>	<span class="c1">// experimental-features.md:119:15</span>
                <span class="n">out_1</span><span class="p">,</span>	<span class="c1">// experimental-features.md:119:15</span>
@@ -211,7 +211,7 @@ <h3 id="vec-literals">Vec Literals</h3>
 <span class="o">}</span>
 </code></pre></div></div>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">VecExample3</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -240,7 +240,7 @@ <h3 id="vec-literals">Vec Literals</h3>
 <span class="o">}</span>
 </code></pre></div></div>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">VecExample5</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">output</span> <span class="p">[</span><span class="mi">7</span><span class="o">:</span><span class="mi">0</span><span class="p">]</span> <span class="n">out_0_foo</span><span class="p">,</span>	<span class="c1">// experimental-features.md:152:15</span>
                <span class="n">out_1_foo</span>	<span class="c1">// experimental-features.md:152:15</span>

chisel3/docs/cookbooks/cookbook.html

@@ -681,7 +681,7 @@ <h3 id="how-do-i-create-io-without-a-prefix">How do I create I/O without a prefi
 <span class="o">}</span>
 </code></pre></div></div>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">MyModule</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -714,7 +714,7 @@ <h3 id="how-do-i-create-io-without-a-prefix">How do I create I/O without a prefi
 
 <p>Note that <code class="language-plaintext highlighter-rouge">io_</code> is nowhere to be seen!</p>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">MyModule</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -750,7 +750,7 @@ <h3 id="how-do-i-minimize-the-number-of-bits-used-in-an-output-vector">How do I
 <p>Unlike <code class="language-plaintext highlighter-rouge">Vecs</code> which represent a singular Chisel type and must have the same width for every element,
 <code class="language-plaintext highlighter-rouge">Seq</code> is a purely Scala construct, so their elements are independent from the perspective of Chisel and can have different widths.</p>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">CountBits</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -878,7 +878,7 @@ <h3 id="how-do-i-get-chisel-to-name-the-results-of-vector-reads-properly">How do
 
 <p>The above code loses the <code class="language-plaintext highlighter-rouge">x</code> name, instead using <code class="language-plaintext highlighter-rouge">_GEN_3</code> (the other <code class="language-plaintext highlighter-rouge">_GEN_*</code> signals are expected).</p>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">Foo</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -903,7 +903,7 @@ <h3 id="how-do-i-get-chisel-to-name-the-results-of-vector-reads-properly">How do
 
 <p>Which produces:</p>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">Foo2</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -947,7 +947,7 @@ <h3 id="how-can-i-dynamically-setparametrize-the-name-of-a-module">How can I dyn
 
 <p>Elaborating the Chisel module <code class="language-plaintext highlighter-rouge">Salt</code> yields our “desired names” for <code class="language-plaintext highlighter-rouge">Salt</code> and <code class="language-plaintext highlighter-rouge">Coffee</code> in the output Verilog:</p>
 
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="c1">// external module Tea</span>
 
 <span class="k">module</span> <span class="n">SodiumMonochloride</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:8:3</span>
@@ -984,7 +984,7 @@ <h3 id="how-do-i-strip-directions-from-a-bidirectional-bundle-or-other-data">How
 </code></pre></div></div>
 
 <div class="language-scala highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="nv">ChiselStage</span><span class="o">.</span><span class="py">emitSystemVerilog</span><span class="o">(</span><span class="k">new</span> <span class="nc">BadRegConnect</span><span class="o">)</span>
-<span class="c1">// circt.stage.phases.Exceptions$FirtoolNonZeroExitCode: firtool returned a non-zero exit code. Note that this version of Chisel (0.0.0+1-a87c9417-SNAPSHOT) was published against firtool version 1.58.0.</span>
+<span class="c1">// circt.stage.phases.Exceptions$FirtoolNonZeroExitCode: firtool returned a non-zero exit code. Note that this version of Chisel (0.0.0+1-1b64e061-SNAPSHOT) was published against firtool version 1.59.0.</span>
 <span class="c1">// ------------------------------------------------------------------------------</span>
 <span class="c1">// ExitCode:</span>
 <span class="c1">// 1</span>

chisel3/docs/cookbooks/dataview.html

@@ -109,7 +109,7 @@ <h3 id="how-do-i-view-a-bundle-as-a-parent-type-superclass">How do I view a Bund
   <span class="nv">bar</span><span class="o">.</span><span class="py">bar</span> <span class="o">:=</span> <span class="mf">123.</span><span class="n">U</span>           <span class="c1">// all fields need to be connected</span>
 <span class="o">}</span>
 </code></pre></div></div>
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">MyModule</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>
@@ -210,7 +210,7 @@ <h3 id="how-can-i-use-viewas-instead-of-viewassupertypetype">How can I use <code
   <span class="nv">bar</span><span class="o">.</span><span class="py">bar</span> <span class="o">:=</span> <span class="mf">123.</span><span class="n">U</span>       <span class="c1">// all fields need to be connected</span>
 <span class="o">}</span>
 </code></pre></div></div>
-<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.58.0</span>
+<div class="language-verilog highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1">// Generated by CIRCT firtool-1.59.0</span>
 <span class="k">module</span> <span class="n">MyModule</span><span class="p">(</span>	<span class="c1">// &lt;stdin&gt;:3:3</span>
   <span class="kt">input</span>        <span class="n">clock</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:4:11</span>
                <span class="n">reset</span><span class="p">,</span>	<span class="c1">// &lt;stdin&gt;:5:11</span>