Added test for #4593

svsim/src/test/resources/SIntWire.sv

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: Apache-2.0
+
+module SIntWire(
+  input signed [31:0] in,
+  output signed [31:0] out);
+
+  assign out = in;//8'h80000000;
+endmodule

svsim/src/test/scala/BackendSpec.scala

@@ -183,6 +183,48 @@ trait BackendSpec extends AnyFunSpec with Matchers {
         val traceReader = new BufferedReader(new FileReader(s"${simulation.workingDirectoryPath}/trace.vcd"))
         traceReader.lines().count() must be > 1L
       }
+
+      it("communicates data correctly") {
+        import Resources._
+        workspace.reset()
+        workspace.elaborateSIntWire()
+        workspace.generateAdditionalSources()
+        simulation = workspace.compile(
+          backend
+        )(
+          workingDirectoryTag = name,
+          commonSettings = CommonCompilationSettings(),
+          backendSpecificSettings = compilationSettings,
+          customSimulationWorkingDirectory = None,
+          verbose = false
+        )
+        simulation.run(
+          verbose = false,
+          executionScriptLimit = None
+        ) { controller =>
+          val in = controller.port("in")
+          val out = controller.port("out")
+
+          controller.setTraceEnabled(true)
+
+          val inVal = 0x80000000
+          val outVal = inVal
+
+          in.set(inVal)
+          in.check(isSigned = true) { value =>
+            assert(value.asBigInt === inVal)
+          }
+          var isOutChecked: Boolean = false
+          out.check(isSigned = true) { value =>
+            isOutChecked = true
+            assert(value.asBigInt === inVal)
+          }
+          assert(isOutChecked === false)
+
+          controller.completeInFlightCommands()
+          assert(isOutChecked === true)
+        }
+      }
     }
   }
 }

svsim/src/test/scala/Resources.scala

@@ -46,5 +46,25 @@ object Resources {
         )
       )
     }
+    def elaborateSIntWire(): Unit = {
+      workspace.addPrimarySourceFromResource(getClass, "/SIntWire.sv")
+      workspace.elaborate(
+        ModuleInfo(
+          name = "SIntWire",
+          ports = Seq(
+            new ModuleInfo.Port(
+              name = "in",
+              isSettable = true,
+              isGettable = true
+            ),
+            new ModuleInfo.Port(
+              name = "out",
+              isSettable = false,
+              isGettable = true
+            )
+          )
+        )
+      )
+    }
   }
 }