[nfc] Run scalafmt on integration tests

Apparently these aren't included in scalafmtAll. Run this for some whitespace cleanup. Signed-off-by: Schuyler Eldridge <[email protected]>
chipsalliance · Nov 11, 2023 · 5d03a5c · 5d03a5c
1 parent 226ea02
commit 5d03a5c
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Showing 3 changed files with 2 additions and 3 deletions.
diff --git a/integration-tests/src/test/scala/chiselTest/MixedVecIntegrationSpec.scala b/integration-tests/src/test/scala/chiselTest/MixedVecIntegrationSpec.scala
@@ -83,7 +83,7 @@ class MixedVecUIntDynamicIndexTester extends BasicTester {
     wire(i) := i.U
   }
 
-  val vecWire = VecInit(wire : Seq[UInt])
+  val vecWire = VecInit(wire: Seq[UInt])
 
   val (cycle, done) = Counter(true.B, n)
   assert(vecWire(cycle) === cycle)

diff --git a/integration-tests/src/test/scala/chiselTest/ShiftRegisterMemSpec.scala b/integration-tests/src/test/scala/chiselTest/ShiftRegisterMemSpec.scala
@@ -31,4 +31,3 @@ class ShiftRegisterMemSpec extends ChiselPropSpec {
     }
   }
 }
-
diff --git a/integration-tests/src/test/scala/chiselTest/util/experimental/TapSpec.scala b/integration-tests/src/test/scala/chiselTest/util/experimental/TapSpec.scala
@@ -43,7 +43,7 @@ class UpDownTest extends BasicTester {
   *       LeftUpper   RightUpper
   *          /           \
   *    LeftLower       RightLower
-  * 
+  *
   * Tap a signal in RightLower from LeftLower and check that it contains the
   * correct value.
   */
Original file line number	Diff line number	Diff line change
Expand Up		@@ -31,4 +31,3 @@ class ShiftRegisterMemSpec extends ChiselPropSpec {
		}
		}
		}