[binder] Support secret ports

chipsalliance · Jan 5, 2024 · 118ed78 · 118ed78
1 parent f6ad9f2
commit 118ed78
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Showing 2 changed files with 19 additions and 3 deletions.
diff --git a/binder/src/main/scala/PanamaCIRCTConverter.scala b/binder/src/main/scala/PanamaCIRCTConverter.scala
@@ -398,6 +398,7 @@ class PanamaCIRCTConverter extends CIRCTConverter {
               case WireBinding(enclosure, visibility)       => rec(enclosure, chain :+ referToValue(data))
               case OpBinding(enclosure, visibility)         => rec(enclosure, chain :+ referToValue(data))
               case RegBinding(enclosure, visibility)        => rec(enclosure, chain :+ referToValue(data))
+              case SecretPortBinding(enclosure)             => rec(enclosure, chain :+ referToPort(data, enclosure))
               case unhandled                                => throw new Exception(s"unhandled binding $unhandled")
             }
           case mem:  Mem[ChiselData]         => chain :+ referToValue(mem.t)
@@ -767,7 +768,7 @@ class PanamaCIRCTConverter extends CIRCTConverter {
   }
 
   def visitDefBlackBox(defBlackBox: DefBlackBox): Unit = {
-    val ports = util.convert(defBlackBox.ports, defBlackBox.topDir)
+    val ports = util.convert(defBlackBox.ports ++ defBlackBox.id.secretPorts, defBlackBox.topDir)
     val nameAttr = circt.mlirStringAttrGet(defBlackBox.name)
 
     val builder = util
@@ -783,7 +784,7 @@ class PanamaCIRCTConverter extends CIRCTConverter {
   }
 
   def visitDefIntrinsicModule(defIntrinsicModule: DefIntrinsicModule): Unit = {
-    val ports = util.convert(defIntrinsicModule.ports, defIntrinsicModule.topDir)
+    val ports = util.convert(defIntrinsicModule.ports ++ defIntrinsicModule.id.secretPorts, defIntrinsicModule.topDir)
 
     val builder = util
       .OpBuilder("firrtl.intmodule", firCtx.circuitBlock, circt.unkLoc)
@@ -802,7 +803,7 @@ class PanamaCIRCTConverter extends CIRCTConverter {
   }
 
   def visitDefModule(defModule: DefModule): Unit = {
-    val ports = util.convert(defModule.ports)
+    val ports = util.convert(defModule.ports ++ defModule.id.secretPorts)
 
     val isMainModule = defModule.id.circuitName == defModule.name
 

diff --git a/binder/src/test/scala/BinderSpec.scala b/binder/src/test/scala/BinderSpec.scala
@@ -8,6 +8,7 @@ import scala.collection.immutable.SeqMap
 import chisel3._
 import chisel3.probe._
 import chisel3.util._
+import chisel3.util.experimental._
 import chisel3.experimental._
 import chisel3.internal.CIRCTConverter
 import chisel3.internal.panama.circt._
@@ -71,6 +72,18 @@ class ProbeSimpleTest extends Module {
   release(a)
 }
 
+class BoreBar extends RawModule {
+  val a = Wire(Bool())
+}
+class BoreBaz(_a: Bool) extends RawModule {
+  val b = Wire(Bool())
+  b := BoringUtils.tapAndRead(_a)
+}
+class BoreTop extends RawModule {
+  val bar = Module(new BoreBar)
+  val baz = Module(new BoreBaz(bar.a))
+}
+
 class BinderTest extends AnyFlatSpec with Matchers {
 
   def streamString(module: => RawModule, stream: CIRCTConverter => Writable): String = Seq(
@@ -152,5 +165,7 @@ class BinderTest extends AnyFlatSpec with Matchers {
       .and(include("release_initial(a)"))
       .and(include("force(clock, _T, a, UInt<1>(0))"))
       .and(include("release(clock, _T_1, a)"))
+
+    firrtlString(new BoreTop) should include("output b_bore")
   }
 }