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run risc-v dv on all branches #294

Merged
merged 25 commits into from
Dec 26, 2024
Merged

run risc-v dv on all branches #294

merged 25 commits into from
Dec 26, 2024

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kgugala
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@kgugala kgugala commented Dec 20, 2024

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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala kgugala force-pushed the custom-riscv-dv-runs branch from 9758e9c to 58f6bac Compare December 20, 2024 13:49
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

2 similar comments
@github-actions GitHub Actions
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@github-actions GitHub Actions
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala kgugala force-pushed the custom-riscv-dv-runs branch from 0f82099 to 496abe1 Compare December 23, 2024 14:09
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

1 similar comment
@github-actions GitHub Actions
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala kgugala force-pushed the custom-riscv-dv-runs branch from e5fcbff to 473b883 Compare December 24, 2024 15:12
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala kgugala force-pushed the custom-riscv-dv-runs branch 2 times, most recently from f8253e4 to 022791a Compare December 26, 2024 13:35
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

kgugala and others added 17 commits December 26, 2024 19:03
@kgugala
tb: tie dangling signals in non-Verilator sim
b791c12
@kgugala
testbench: ahb_sif: initialize bvalid
95ea2d3
@kgugala
run custom coverage in PRs
b038714
@kgugala
verif:exu_mul: tie inputs to gnd on reset
fe21934
@kgugala
verif: exu_div: tie input to gnd on reset
93abf5a
@kgugala
verif: pic: tie inputs to gnd on reset
88a1bdc
@kgugala
verif: dma: tie inputs to gnd on reset
5e3fb25
@kgugala
verif: dma: set clk_en=1
f5396b8
@kgugala
verif: axi_to_ahb: initialize inputs
9439036
@kgugala
verif: axi_to_ahb: wait for reset before looping
d133540
@kgugala
verif: ahb_2_axi: initialize inputs
177edfc
@kgugala
verif: dmi: fix space define and wait for reset before looping
4e78cdd
@kgugala
verif: iccm: remove multidrivers, initialize signals on reset
633b7e5
@kgugala
verif: dccm: fix multidriven
bb9a2f0
@kgugala
verif: dma: do not set cmd_type in reset
b5baa0c
@kgugala
CI: add custom uarch tests step
fffc16c
@tmichalak @kgugala
verification: ahb_sif: Use legal index value
86e3295
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala kgugala force-pushed the custom-riscv-dv-runs branch from c56250f to b6a0c77 Compare December 26, 2024 18:35
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Links to coverage and verification reports for this PR (#294) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

@kgugala kgugala merged commit a0a2e22 into main Dec 26, 2024
438 checks passed
@kgugala kgugala deleted the custom-riscv-dv-runs branch December 26, 2024 20:30
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@kgugala @tmichalak