fix icache

.github/workflows/test-regression.yml

@@ -13,7 +13,8 @@ jobs:
       matrix:
         bus: ["axi", "ahb"]
         test: ["hello_world", "hello_world_dccm", "hello_world_iccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "ecc",
-               "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", "write_unaligned"]
+               "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", "write_unaligned",
+               "icache"]
         coverage: ["branch", "toggle"] #TODO: add functional coverage
         priv: ["0", "1"]
         exclude:

design/ifu/el2_ifu_ic_mem.sv

@@ -297,7 +297,7 @@ import el2_pkg::*;
 
         // Use exported ICache interface.
         always_comb begin
-          wb_dout_pre_up = icache_export.wb_dout_pre_up;
+          wb_dout_pre_up[i][k] = icache_export.wb_dout_pre_up[i][k];
         end
         if (pt.ICACHE_BYPASS_ENABLE == 1) begin
           assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (pt.ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1);
@@ -358,7 +358,7 @@ import el2_pkg::*;
 
         // Use exported ICache interface.
         always_comb begin
-           wb_dout_pre_up = icache_export.wb_dout_pre_up;
+           wb_dout_pre_up[i][k][68-1:0] = icache_export.wb_dout_pre_up[i][k][68-1:0];
         end
         if (pt.ICACHE_BYPASS_ENABLE == 1) begin
           assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (pt.ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1);
@@ -439,8 +439,8 @@ import el2_pkg::*;
 
         // Use exported ICache interface.
         always_comb begin
-          icache_export.ic_b_sb_bit_en_vec = ic_b_sb_bit_en_vec;
-          wb_packeddout_pre = icache_export.wb_packeddout_pre;
+          icache_export.ic_b_sb_bit_en_vec[k] = ic_b_sb_bit_en_vec[k];
+          wb_packeddout_pre[k] = icache_export.wb_packeddout_pre[k];
         end
 
         for (genvar i=0; i<pt.ICACHE_NUM_WAYS; i++) begin: BITEN
@@ -519,8 +519,8 @@ import el2_pkg::*;
 
         // Use exported ICache interface.
         always_comb begin
-           icache_export.ic_b_sb_bit_en_vec = ic_b_sb_bit_en_vec;
-           wb_packeddout_pre = icache_export.wb_packeddout_pre;
+           icache_export.ic_b_sb_bit_en_vec[k] = ic_b_sb_bit_en_vec[k];
+           wb_packeddout_pre[k] = icache_export.wb_packeddout_pre[k];
         end
 
         for (genvar i=0; i<pt.ICACHE_NUM_WAYS; i++) begin: BITEN

design/lib/el2_mem_if.sv

@@ -22,8 +22,6 @@ import el2_pkg::*;
 interface el2_mem_if #(
     `include "el2_param.vh"
 ) ();
-  localparam DCCM_ECC_WIDTH = pt.DCCM_FDATA_WIDTH - pt.DCCM_DATA_WIDTH;
-
   //////////////////////////////////////////
   // Clock
   logic                                                               clk;
@@ -47,9 +45,9 @@ interface el2_mem_if #(
   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_wren_bank;
   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
-  logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
+  logic [pt.DCCM_NUM_BANKS-1:0][               pt.DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;
-  logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_bank_ecc;
+  logic [pt.DCCM_NUM_BANKS-1:0][               pt.DCCM_ECC_WIDTH-1:0] dccm_bank_ecc;
 
   //////////////////////////////////////////
   // ICACHE DATA

testbench/asm/icache.ld

@@ -0,0 +1,8 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS {
+  .text  :  { *(.text*) }
+  . = 0x10000;
+  .data  :  { *(.*data) *(.rodata*)}
+}

testbench/asm/icache.s

@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2024 Antmicro <www.antmicro.com>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+    .set    mfdc, 0x7f9
+    .set    mrac, 0x7c0
+// Code to execute
+.section .text
+.global _start
+_start:
+    // Enable Caches in MRAC
+    li x1, 0x5f555555
+    csrw    mrac, x1
+    li  x3, 4
+    csrw    mfdc, x3        // disable store merging
+
+    li      t3,  0   // counter for the outer loop
+    li      t5,  100 // limit the outer loop to 100 iterations
+outer:
+    beq t3, t5, report_success
+    addi    t3, t3, 1
+    li      t4, 123
+inner:
+    addi    t4, t4, -1
+    bne     t4, zero, inner
+    jal     x0, outer
+report_success:
+    // write 0xff to STDOUT to report success
+    li      x3, STDOUT
+    li      x2, 0xff
+    sw      x2, 0(x3)
+end:
+    nop
+    j end
+.long   0,1,2,3,4

testbench/tb_top.sv

@@ -2290,7 +2290,7 @@ end : Gen_iccm_enable
  end // block: PACKED_0
 
  // WAY PACKED
- else begin : PACKED_1
+ else begin : PACKED_10
 
  // generate IC DATA PACKED SRAMS for 2/4 ways
   for (genvar k=0; k<pt.ICACHE_BANKS_WAY; k++) begin: BANKS_WAY   // 16B subbank
@@ -2337,8 +2337,7 @@ end : Gen_iccm_enable
               `EL2_PACKED_IC_DATA_SRAM(512,284,71,k)
            end // block: WAYS
            else   begin : WAYS
-              // TODO bring back
-              // `EL2_PACKED_IC_DATA_SRAM(512,142,71,k)
+              `EL2_PACKED_IC_DATA_SRAM(512,142,71,k)
            end // block: WAYS
         end // block: size_512
 
@@ -2445,7 +2444,7 @@ end : Gen_iccm_enable
         end // block: size_64
      end // block: ECC0
      end // block: BANKS_WAY
- end // block: PACKED_1
+ end // block: PACKED_10
 
 
 // ICACHE TAG