Add insertion of include guards to VeeR config files, move assert enable flag to Makefile #154
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Internal-tag: [#52140] Signed-off-by: Maciej Kurc <[email protected]> Signed-off-by: Rafal Kolucki <[email protected]>
Internal-tag: [#52140] Signed-off-by: Rafal Kolucki <[email protected]>
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Links to coverage and verification reports for this PR (#154) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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LGTM |
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Fixes #150.
Changes:
veer.confignow adds guards to the generated Verilog include files to prevent multiple inclusion in RTLassert=1argument to Makefile while running simulations instead of using configuration flag.