[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer.sv:26:-`include "el2_param.vh" design/el2_veer.sv:27:- ) design/el2_veer.sv:28:- ( design/el2_veer.sv:29:- input logic clk, design/el2_veer.sv:30:- input logic rst_l, design/el2_veer.sv:31:- input logic dbg_rst_l, design/el2_veer.sv:32:- input logic [31:1] rst_vec, design/el2_veer.sv:33:- input logic nmi_int, design/el2_veer.sv:34:- input logic [31:1] nmi_vec, design/el2_veer.sv:35:- output logic core_rst_l, // This is "rst_l | dbg_rst_l" design/el2_veer.sv:36:- design/el2_veer.sv:37:- output logic active_l2clk, design/el2_veer.sv:38:- output logic free_l2clk, design/el2_veer.sv:39:- design/el2_veer.sv:40:- output logic [31:0] trace_rv_i_insn_ip, design/el2_veer.sv:41:- output logic [31:0] trace_rv_i_address_ip, design/el2_veer.sv:42:- output logic trace_rv_i_valid_ip, design/el2_veer.sv:43:- output logic trace_rv_i_exception_ip, design/el2_veer.sv:44:- output logic [4:0] trace_rv_i_ecause_ip, design/el2_veer.sv:45:- output logic trace_rv_i_interrupt_ip, design/el2_veer.sv:46:- output logic [31:0] trace_rv_i_tval_ip, design/el2_veer.sv:47:- design/el2_veer.sv:48:- design/el2_veer.sv:49:- output logic dccm_clk_override, design/el2_veer.sv:50:- output logic icm_clk_override, design/el2_veer.sv:51:- output logic dec_tlu_core_ecc_disable, design/el2_veer.sv:52:- design/el2_veer.sv:53:- // external halt/run interface design/el2_veer.sv:54:- input logic i_cpu_halt_req, // Asynchronous Halt request to CPU design/el2_veer.sv:55:- input logic i_cpu_run_req, // Asynchronous Restart request to CPU design/el2_veer.sv:56:- output logic o_cpu_halt_ack, // Core Acknowledge to Halt request design/el2_veer.sv:57:- output logic o_cpu_halt_status, // 1'b1 indicates processor is halted design/el2_veer.sv:58:- output logic o_cpu_run_ack, // Core Acknowledge to run request design/el2_veer.sv:59:- output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request design/el2_veer.sv:60:- design/el2_veer.sv:61:- input logic [31:4] core_id, // CORE ID design/el2_veer.sv:62:- design/el2_veer.sv:63:- // external MPC halt/run interface design/el2_veer.sv:64:- input logic mpc_debug_halt_req, // Async halt request design/el2_veer.sv:65:- input logic mpc_debug_run_req, // Async run request design/el2_veer.sv:66:- input logic mpc_reset_run_req, // Run/halt after reset design/el2_veer.sv:67:- output logic mpc_debug_halt_ack, // Halt ack design/el2_veer.sv:68:- output logic mpc_debug_run_ack, // Run ack design/el2_veer.sv:69:- output logic debug_brkpt_status, // debug breakpoint design/el2_veer.sv:70:- design/el2_veer.sv:71:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc design/el2_veer.sv:72:- output logic dec_tlu_perfcnt1, design/el2_veer.sv:73:- output logic dec_tlu_perfcnt2, design/el2_veer.sv:74:- output logic dec_tlu_perfcnt3, design/el2_veer.sv:75:- design/el2_veer.sv:76:- // DCCM ports design/el2_veer.sv:77:- output logic dccm_wren, design/el2_veer.sv:78:- output logic dccm_rden, design/el2_veer.sv:79:- output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, design/el2_veer.sv:80:- output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, design/el2_veer.sv:81:- output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, design/el2_veer.sv:82:- output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, design/el2_veer.sv:83:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, design/el2_veer.sv:84:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, design/el2_veer.sv:85:- design/el2_veer.sv:86:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, design/el2_veer.sv

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer.sv:395:- logic [63:0] hwdata_nc; design/el2_veer.sv:396:- //---------------------------------------------------------------------- design/el2_veer.sv:397:- // design/el2_veer.sv:398:- //---------------------------------------------------------------------- design/el2_veer.sv:399:- design/el2_veer.sv:400:- logic ifu_pmu_instr_aligned; design/el2_veer.sv:401:- logic ifu_ic_error_start; design/el2_veer.sv:402:- logic ifu_iccm_dma_rd_ecc_single_err; design/el2_veer.sv:403:- logic ifu_iccm_rd_ecc_single_err; design/el2_veer.sv:404:- logic ifu_iccm_rd_ecc_double_err; design/el2_veer.sv:405:- logic lsu_dccm_rd_ecc_single_err; design/el2_veer.sv:406:- logic lsu_dccm_rd_ecc_double_err; design/el2_veer.sv:407:- design/el2_veer.sv:408:- logic lsu_axi_awready_ahb; design/el2_veer.sv:409:- logic lsu_axi_wready_ahb; design/el2_veer.sv:410:- logic lsu_axi_bvalid_ahb; design/el2_veer.sv:411:- logic lsu_axi_bready_ahb; design/el2_veer.sv:412:- logic [1:0] lsu_axi_bresp_ahb; design/el2_veer.sv:413:- logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_ahb; design/el2_veer.sv:414:- logic lsu_axi_arready_ahb; design/el2_veer.sv:415:- logic lsu_axi_rvalid_ahb; design/el2_veer.sv:416:- logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_ahb; design/el2_veer.sv:417:- logic [63:0] lsu_axi_rdata_ahb; design/el2_veer.sv:418:- logic [1:0] lsu_axi_rresp_ahb; design/el2_veer.sv:419:- logic lsu_axi_rlast_ahb; design/el2_veer.sv:420:- design/el2_veer.sv:421:- logic lsu_axi_awready_int; design/el2_veer.sv:422:- logic lsu_axi_wready_int; design/el2_veer.sv:423:- logic lsu_axi_bvalid_int; design/el2_veer.sv:424:- logic lsu_axi_bready_int; design/el2_veer.sv:425:- logic [1:0] lsu_axi_bresp_int; design/el2_veer.sv:426:- logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_int; design/el2_veer.sv:427:- logic lsu_axi_arready_int; design/el2_veer.sv:428:- logic lsu_axi_rvalid_int; design/el2_veer.sv:429:- logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_int; design/el2_veer.sv:430:- logic [63:0] lsu_axi_rdata_int; design/el2_veer.sv:431:- logic [1:0] lsu_axi_rresp_int; design/el2_veer.sv:432:- logic lsu_axi_rlast_int; design/el2_veer.sv:433:- design/el2_veer.sv:434:- logic ifu_axi_awready_ahb; design/el2_veer.sv:435:- logic ifu_axi_wready_ahb; design/el2_veer.sv:436:- logic ifu_axi_bvalid_ahb; design/el2_veer.sv:437:- logic ifu_axi_bready_ahb; design/el2_veer.sv:438:- logic [1:0] ifu_axi_bresp_ahb; design/el2_veer.sv:439:- logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_ahb; design/el2_veer.sv:440:- logic ifu_axi_arready_ahb; design/el2_veer.sv:441:- logic ifu_axi_rvalid_ahb; design/el2_veer.sv:442:- logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_ahb; design/el2_veer.sv:443:- logic [63:0] ifu_axi_rdata_ahb; design/el2_veer.sv:444:- logic [1:0] ifu_axi_rresp_ahb; design/el2_veer.sv:445:- logic ifu_axi_rlast_ahb; design/el2_veer.sv:446:- design/el2_veer.sv:447:- logic ifu_axi_awready_int; design/el2_veer.sv:448:- logic ifu_axi_wready_int; design/el2_veer.sv:449:- logic ifu_axi_bvalid_int; design/el2_veer.sv:450:- logic

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer.sv:883:- // ----------------- DEBUG END ----------------------------- design/el2_veer.sv:884:- design/el2_veer.sv:885:- assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode); design/el2_veer.sv:886:- design/el2_veer.sv:887:- // fetch design/el2_veer.sv:888:- el2_ifu #(.pt(pt)) ifu ( design/el2_veer.sv:889:- .clk(active_l2clk), design/el2_veer.sv:890:- .rst_l(core_rst_l), design/el2_veer.sv:891:- .dec_tlu_flush_err_wb (dec_tlu_flush_err_r ), design/el2_veer.sv:892:- .dec_tlu_flush_noredir_wb (dec_tlu_flush_noredir_r ), design/el2_veer.sv:893:- .dec_tlu_fence_i_wb (dec_tlu_fence_i_r ), design/el2_veer.sv:894:- .dec_tlu_flush_leak_one_wb (dec_tlu_flush_leak_one_r ), design/el2_veer.sv:895:- .dec_tlu_flush_lower_wb (dec_tlu_flush_lower_r ), design/el2_veer.sv:896:- design/el2_veer.sv:897:- // AXI signals design/el2_veer.sv:898:- .ifu_axi_arready(ifu_axi_arready_int), design/el2_veer.sv:899:- .ifu_axi_rvalid(ifu_axi_rvalid_int), design/el2_veer.sv:900:- .ifu_axi_rid(ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0]), design/el2_veer.sv:901:- .ifu_axi_rdata(ifu_axi_rdata_int[63:0]), design/el2_veer.sv:902:- .ifu_axi_rresp(ifu_axi_rresp_int[1:0]), design/el2_veer.sv:903:- design/el2_veer.sv:904:- .* design/el2_veer.sv:905:- ); design/el2_veer.sv:906:- design/el2_veer.sv:907:- design/el2_veer.sv:908:- assign iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || ifu_iccm_dma_rd_ecc_single_err; design/el2_veer.sv:909:- assign iccm_ecc_double_error = ifu_iccm_rd_ecc_double_err; design/el2_veer.sv:910:- design/el2_veer.sv:911:- el2_dec #(.pt(pt)) dec ( design/el2_veer.sv:912:- .clk(active_l2clk), design/el2_veer.sv:913:- .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]), design/el2_veer.sv:914:- .rst_l(core_rst_l), design/el2_veer.sv:915:- .* design/el2_veer.sv:916:- ); design/el2_veer.sv:917:- design/el2_veer.sv:918:- el2_exu #(.pt(pt)) exu ( design/el2_veer.sv:919:- .clk(active_l2clk), design/el2_veer.sv:920:- .rst_l(core_rst_l), design/el2_veer.sv:921:- .* design/el2_veer.sv:922:- ); design/el2_veer.sv:923:- design/el2_veer.sv:924:- el2_lsu #(.pt(pt)) lsu ( design/el2_veer.sv:925:- .clk(active_l2clk), design/el2_veer.sv:926:- .rst_l(core_rst_l), design/el2_veer.sv:927:- .clk_override(dec_tlu_lsu_clk_override), design/el2_veer.sv:928:- .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r), design/el2_veer.sv:929:- design/el2_veer.sv:930:- // AXI signals design/el2_veer.sv:931:- .lsu_axi_awready(lsu_axi_awready_int), design/el2_veer.sv:932:- .lsu_axi_wready(lsu_axi_wready_int), design/el2_veer.sv:933:- .lsu_axi_bvalid(lsu_axi_bvalid_int), design/el2_veer.sv:934:- .lsu_axi_bid(lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0]), design/el2_veer.sv:935:- .lsu_axi_bresp(lsu_axi_bresp_int[1:0]), design/el2_veer.sv:936:- design/el2_veer.sv:937:- .lsu_axi_arready(lsu_axi_arready_int), design/el2_veer.sv:938:- .lsu_axi_rvalid(lsu_axi_rvalid_int), design/el2_veer.sv:939:- .lsu_axi_rid(lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0]), design/el2_veer.sv:940:-

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:288:- // clk ratio signals design/el2_veer_wrapper.sv:289:- input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:290:- input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:291:- input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:292:- input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface design/el2_veer_wrapper.sv:293:- design/el2_veer_wrapper.sv:294:- // ICCM/DCCM ECC status design/el2_veer_wrapper.sv:295:- output logic iccm_ecc_single_error, design/el2_veer_wrapper.sv:296:- output logic iccm_ecc_double_error, design/el2_veer_wrapper.sv:297:- output logic dccm_ecc_single_error, design/el2_veer_wrapper.sv:298:- output logic dccm_ecc_double_error, design/el2_veer_wrapper.sv:299:- design/el2_veer_wrapper.sv:300:- // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not) design/el2_veer_wrapper.sv:301:- design/el2_veer_wrapper.sv:302:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, design/el2_veer_wrapper.sv:303:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, design/el2_veer_wrapper.sv:304:- design/el2_veer_wrapper.sv:305:- input logic timer_int, design/el2_veer_wrapper.sv:306:- input logic soft_int, design/el2_veer_wrapper.sv:307:- input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, design/el2_veer_wrapper.sv:308:- design/el2_veer_wrapper.sv:309:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc design/el2_veer_wrapper.sv:310:- output logic dec_tlu_perfcnt1, design/el2_veer_wrapper.sv:311:- output logic dec_tlu_perfcnt2, design/el2_veer_wrapper.sv:312:- output logic dec_tlu_perfcnt3, design/el2_veer_wrapper.sv:313:- design/el2_veer_wrapper.sv:314:- // ports added by the soc team design/el2_veer_wrapper.sv:315:- input logic jtag_tck, // JTAG clk design/el2_veer_wrapper.sv:316:- input logic jtag_tms, // JTAG TMS design/el2_veer_wrapper.sv:317:- input logic jtag_tdi, // JTAG tdi design/el2_veer_wrapper.sv:318:- input logic jtag_trst_n, // JTAG Reset design/el2_veer_wrapper.sv:319:- output logic jtag_tdo, // JTAG TDO design/el2_veer_wrapper.sv:320:- design/el2_veer_wrapper.sv:321:- input logic [31:4] core_id, design/el2_veer_wrapper.sv:322:- design/el2_veer_wrapper.sv:323:- // Memory Export Interface design/el2_veer_wrapper.sv:324:- el2_mem_if.veer_sram_src el2_mem_export, design/el2_veer_wrapper.sv:325:- design/el2_veer_wrapper.sv:326:- // external MPC halt/run interface design/el2_veer_wrapper.sv:327:- input logic mpc_debug_halt_req, // Async halt request design/el2_veer_wrapper.sv:328:- input logic mpc_debug_run_req, // Async run request design/el2_veer_wrapper.sv:329:- input logic mpc_reset_run_req, // Run/halt after reset design/el2_veer_wrapper.sv:330:- output logic mpc_debug_halt_ack, // Halt ack design/el2_veer_wrapper.sv:331:- output logic mpc_debug_run_ack, // Run ack design/el2_veer_wrapper.sv:332:- outpu

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu.sv:25:-`include "el2_param.vh" design/ifu/el2_ifu.sv:26:- ) design/ifu/el2_ifu.sv:27:- ( design/ifu/el2_ifu.sv:28:- input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. design/ifu/el2_ifu.sv:29:- input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/ifu/el2_ifu.sv:30:- input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/ifu/el2_ifu.sv:31:- input logic rst_l, // reset, active low design/ifu/el2_ifu.sv:32:- design/ifu/el2_ifu.sv:33:- input logic dec_i0_decode_d, // Valid instruction at D and not blocked design/ifu/el2_ifu.sv:34:- design/ifu/el2_ifu.sv:35:- input logic exu_flush_final, // flush, includes upper and lower design/ifu/el2_ifu.sv:36:- input logic dec_tlu_i0_commit_cmt , // committed i0 design/ifu/el2_ifu.sv:37:- input logic dec_tlu_flush_err_wb , // flush due to parity error. design/ifu/el2_ifu.sv:38:- input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final design/ifu/el2_ifu.sv:39:- input logic [31:1] exu_flush_path_final, // flush fetch address design/ifu/el2_ifu.sv:40:- design/ifu/el2_ifu.sv:41:- input logic [31:0] dec_tlu_mrac_ff ,// Side_effect , cacheable for each region design/ifu/el2_ifu.sv:42:- input logic dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final design/ifu/el2_ifu.sv:43:- input logic dec_tlu_flush_leak_one_wb, // ignore bp for leak one fetches design/ifu/el2_ifu.sv:44:- design/ifu/el2_ifu.sv:45:- input logic dec_tlu_bpred_disable, // disable all branch prediction design/ifu/el2_ifu.sv:46:- input logic dec_tlu_core_ecc_disable, // disable ecc checking and flagging design/ifu/el2_ifu.sv:47:- input logic dec_tlu_force_halt, // force halt design/ifu/el2_ifu.sv:48:- design/ifu/el2_ifu.sv:49:- //-------------------------- IFU AXI signals-------------------------- design/ifu/el2_ifu.sv:50:- // AXI Write Channels design/ifu/el2_ifu.sv:51:- output logic ifu_axi_awvalid, design/ifu/el2_ifu.sv:52:- output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid, design/ifu/el2_ifu.sv:53:- output logic [31:0] ifu_axi_awaddr, design/ifu/el2_ifu.sv:54:- output logic [3:0] ifu_axi_awregion, design/ifu/el2_ifu.sv:55:- output logic [7:0] ifu_axi_awlen, design/ifu/el2_ifu.sv:56:- output logic [2:0] ifu_axi_awsize, design/ifu/el2_ifu.sv:57:- output logic [1:0] ifu_axi_awburst, design/ifu/el2_ifu.sv:58:- output logic ifu_axi_awlock, design/ifu/el2_ifu.sv:59:- output logic [3:0] ifu_axi_awcache, design/ifu/el2_ifu.sv:60:- output logic [2:0] ifu_axi_awprot, design/ifu/el2_ifu.sv:61:- output logic [3:0] ifu_axi_awqos, design/ifu/el2_ifu.sv:62:- design/ifu/el2_ifu.sv:63:- output logic ifu_axi_wvalid, design/ifu/el2_ifu.sv:64:- output logic [63:0] ifu_axi_wdata, design/ifu/el2_ifu.sv:65:- output logic [7:0] ifu_axi_wstrb, design/ifu/el2_ifu.sv:66:- output logic ifu_axi_wlast, design/ifu/el2_ifu.sv:67:- design/ifu/el2_ifu.sv:68:- output logic ifu_axi_bready, design/ifu/el2_ifu.sv:69:- design/ifu/el2_ifu.sv:70:- // AXI Read Channels design/ifu/el2_ifu.sv:71:- output logic ifu_axi_arvalid, design/ifu/el2_ifu.sv:72:- input logic ifu_axi_arready, design/ifu/el2_ifu.sv:73:- ou

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu.sv:219:- logic [1:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch design/ifu/el2_ifu.sv:220:- logic [31:1] ifu_fetch_pc; // starting pc of fetch design/ifu/el2_ifu.sv:221:- design/ifu/el2_ifu.sv:222:- logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start; design/ifu/el2_ifu.sv:223:- assign ifu_iccm_dma_rd_ecc_single_err = iccm_dma_rd_ecc_single_err; design/ifu/el2_ifu.sv:224:- assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err; design/ifu/el2_ifu.sv:225:- assign ifu_ic_error_start = ic_error_start; design/ifu/el2_ifu.sv:226:- design/ifu/el2_ifu.sv:227:- design/ifu/el2_ifu.sv:228:- logic ic_write_stall; design/ifu/el2_ifu.sv:229:- logic ic_dma_active; design/ifu/el2_ifu.sv:230:- logic ifc_dma_access_ok; design/ifu/el2_ifu.sv:231:- logic [1:0] ic_access_fault_f; design/ifu/el2_ifu.sv:232:- logic [1:0] ic_access_fault_type_f; design/ifu/el2_ifu.sv:233:- logic ifu_ic_mb_empty; design/ifu/el2_ifu.sv:234:- design/ifu/el2_ifu.sv:235:- logic ic_hit_f; design/ifu/el2_ifu.sv:236:- design/ifu/el2_ifu.sv:237:- logic [1:0] ifu_bp_way_f; // way indication; right justified design/ifu/el2_ifu.sv:238:- logic ifu_bp_hit_taken_f; // kill next fetch; taken target found design/ifu/el2_ifu.sv:239:- logic [31:1] ifu_bp_btb_target_f; // predicted target PC design/ifu/el2_ifu.sv:240:- logic ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified design/ifu/el2_ifu.sv:241:- logic [1:0] ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified design/ifu/el2_ifu.sv:242:- logic [1:0] ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified design/ifu/el2_ifu.sv:243:- logic [11:0] ifu_bp_poffset_f; // predicted target design/ifu/el2_ifu.sv:244:- logic [1:0] ifu_bp_ret_f; // predicted ret ; right justified design/ifu/el2_ifu.sv:245:- logic [1:0] ifu_bp_pc4_f; // pc4 indication; right justified design/ifu/el2_ifu.sv:246:- logic [1:0] ifu_bp_valid_f; // branch valid, right justified design/ifu/el2_ifu.sv:247:- logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f; design/ifu/el2_ifu.sv:248:- logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f; design/ifu/el2_ifu.sv:249:- design/ifu/el2_ifu.sv:250:- design/ifu/el2_ifu.sv:251:- logic [1:0] ic_fetch_val_f; design/ifu/el2_ifu.sv:252:- logic [31:0] ic_data_f; design/ifu/el2_ifu.sv:253:- logic [31:0] ifu_fetch_data_f; design/ifu/el2_ifu.sv:254:- logic ifc_fetch_req_f; design/ifu/el2_ifu.sv:255:- logic ifc_fetch_req_f_raw; design/ifu/el2_ifu.sv:256:- logic iccm_dma_rd_ecc_double_err; design/ifu/el2_ifu.sv:257:- logic [1:0] iccm_rd_ecc_double_err; // This fetch has an iccm double error. design/ifu/el2_ifu.sv:258:- assign ifu_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err || |iccm_dma_rd_ecc_double_err; design/ifu/el2_ifu.sv:259:- design/ifu/el2_ifu.sv:260:- logic ifu_async_error_start; design/ifu/el2_ifu.sv:261:- design/ifu/el2_ifu.sv:262:- design/ifu/el2_ifu.sv:263:- assign ifu_fetch_data_f[31:0] = ic_data_f[31:0]; design/ifu/el2_ifu.sv:264:- assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0]; design/ifu/el2_ifu.sv:265:- assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1]; design/ifu/el2_ifu.sv:266:- design/ifu/el2_ifu.sv:267:- logic ifc_fetch_uncacheable_bf; // The fetch request is uncacheable space. BF stage design/ifu/el2_ifu.sv:268:- logic ifc_fetch_req_bf; // Fetch request. Comes with the address. BF stage design/ifu/el2_ifu.sv:269:- logic ifc_fetch_req_bf_raw; // Fetch request without some qualifications. Used for clock-gating. BF stage design/ifu/el2_ifu.sv:270:- logic ifc_iccm_access_bf; // This request is to the ICCM. Do not generate misses to the bus. design/ifu/el2_ifu.sv:271:- logic ifc_region_acc_fau

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_mem_ctl.sv:27:-`include "el2_param.vh" design/ifu/el2_ifu_mem_ctl.sv:28:- ) design/ifu/el2_ifu_mem_ctl.sv:29:- ( design/ifu/el2_ifu_mem_ctl.sv:30:- input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/ifu/el2_ifu_mem_ctl.sv:31:- input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/ifu/el2_ifu_mem_ctl.sv:32:- input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. design/ifu/el2_ifu_mem_ctl.sv:33:- input logic rst_l, // reset, active low design/ifu/el2_ifu_mem_ctl.sv:34:- design/ifu/el2_ifu_mem_ctl.sv:35:- input logic exu_flush_final, // Flush from the pipeline., includes flush lower design/ifu/el2_ifu_mem_ctl.sv:36:- input logic dec_tlu_flush_lower_wb, // Flush lower from the pipeline. design/ifu/el2_ifu_mem_ctl.sv:37:- input logic dec_tlu_flush_err_wb, // Flush from the pipeline due to perr. design/ifu/el2_ifu_mem_ctl.sv:38:- input logic dec_tlu_i0_commit_cmt, // committed i0 instruction design/ifu/el2_ifu_mem_ctl.sv:39:- input logic dec_tlu_force_halt, // force halt. design/ifu/el2_ifu_mem_ctl.sv:40:- design/ifu/el2_ifu_mem_ctl.sv:41:- input logic [31:1] ifc_fetch_addr_bf, // Fetch Address byte aligned always. F1 stage. design/ifu/el2_ifu_mem_ctl.sv:42:- input logic ifc_fetch_uncacheable_bf, // The fetch request is uncacheable space. F1 stage design/ifu/el2_ifu_mem_ctl.sv:43:- input logic ifc_fetch_req_bf, // Fetch request. Comes with the address. F1 stage design/ifu/el2_ifu_mem_ctl.sv:44:- input logic ifc_fetch_req_bf_raw, // Fetch request without some qualifications. Used for clock-gating. F1 stage design/ifu/el2_ifu_mem_ctl.sv:45:- input logic ifc_iccm_access_bf, // This request is to the ICCM. Do not generate misses to the bus. design/ifu/el2_ifu_mem_ctl.sv:46:- input logic ifc_region_acc_fault_bf, // Access fault. in ICCM region but offset is outside defined ICCM. design/ifu/el2_ifu_mem_ctl.sv:47:- input logic ifc_dma_access_ok, // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle). design/ifu/el2_ifu_mem_ctl.sv:48:- input logic dec_tlu_fence_i_wb, // Fence.i instruction is committing. Clear all Icache valids. design/ifu/el2_ifu_mem_ctl.sv:49:- input logic ifu_bp_hit_taken_f, // Branch is predicted taken. Kill the fetch next cycle. design/ifu/el2_ifu_mem_ctl.sv:50:- design/ifu/el2_ifu_mem_ctl.sv:51:- input logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified design/ifu/el2_ifu_mem_ctl.sv:52:- design/ifu/el2_ifu_mem_ctl.sv:53:- output logic ifu_miss_state_idle, // No icache misses are outstanding. design/ifu/el2_ifu_mem_ctl.sv:54:- output logic ifu_ic_mb_empty, // Continue with normal fetching. This does not mean that miss is finished. design/ifu/el2_ifu_mem_ctl.sv:55:- output logic ic_dma_active , // In the middle of servicing dma request to ICCM. Do not make any new requests. design/ifu/el2_ifu_mem_ctl.sv:56:- output logic ic_write_stall, // Stall fetch the cycle we are writing th

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_mem_ctl.sv:1288:-///////////////////////////////////////////////////////////////////////////////////// design/ifu/el2_ifu_mem_ctl.sv:1289:-// ECC checking logic for ICCM data. // design/ifu/el2_ifu_mem_ctl.sv:1290:-///////////////////////////////////////////////////////////////////////////////////// design/ifu/el2_ifu_mem_ctl.sv:1577:+ ///////////////////////////////////////////////////////////////////////////////////// design/ifu/el2_ifu_mem_ctl.sv:1578:+ // ECC checking logic for ICCM data. // design/ifu/el2_ifu_mem_ctl.sv:1579:+ /////////////////////////////////////////////////////////////////////////////////////

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/lsu/el2_lsu.sv:31:-`include "el2_param.vh" design/lsu/el2_lsu.sv:32:- ) design/lsu/el2_lsu.sv:33:-( design/lsu/el2_lsu.sv:34:- design/lsu/el2_lsu.sv:35:- input logic clk_override, // Override non-functional clock gating design/lsu/el2_lsu.sv:36:- input logic dec_tlu_flush_lower_r, // I0/I1 writeback flush. This is used to flush the old packets only design/lsu/el2_lsu.sv:37:- input logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state design/lsu/el2_lsu.sv:38:- input logic dec_tlu_force_halt, // This will be high till TLU goes to debug halt design/lsu/el2_lsu.sv:39:- design/lsu/el2_lsu.sv:40:- // chicken signals design/lsu/el2_lsu.sv:41:- input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals design/lsu/el2_lsu.sv:42:- input logic dec_tlu_wb_coalescing_disable, // disable the write buffer coalesce design/lsu/el2_lsu.sv:43:- input logic dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus design/lsu/el2_lsu.sv:44:- input logic dec_tlu_core_ecc_disable, // disable the generation of the ecc design/lsu/el2_lsu.sv:45:- design/lsu/el2_lsu.sv:46:- input logic [31:0] exu_lsu_rs1_d, // address rs operand design/lsu/el2_lsu.sv:47:- input logic [31:0] exu_lsu_rs2_d, // store data design/lsu/el2_lsu.sv:48:- input logic [11:0] dec_lsu_offset_d, // address offset operand design/lsu/el2_lsu.sv:49:- design/lsu/el2_lsu.sv:50:- input el2_lsu_pkt_t lsu_p, // lsu control packet design/lsu/el2_lsu.sv:51:- input logic dec_lsu_valid_raw_d, // Raw valid for address computation design/lsu/el2_lsu.sv:52:- input logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control design/lsu/el2_lsu.sv:53:- design/lsu/el2_lsu.sv:54:- output logic [31:0] lsu_result_m, // lsu load data design/lsu/el2_lsu.sv:55:- output logic [31:0] lsu_result_corr_r, // This is the ECC corrected data going to RF design/lsu/el2_lsu.sv:56:- output logic lsu_load_stall_any, // This is for blocking loads in the decode design/lsu/el2_lsu.sv:57:- output logic lsu_store_stall_any, // This is for blocking stores in the decode design/lsu/el2_lsu.sv:58:- output logic lsu_fastint_stall_any, // Stall the fastint in decode-1 stage design/lsu/el2_lsu.sv:59:- output logic lsu_idle_any, // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA design/lsu/el2_lsu.sv:60:- output logic lsu_active, // Used to turn off top level clk design/lsu/el2_lsu.sv:61:- design/lsu/el2_lsu.sv:62:- output logic [31:1] lsu_fir_addr, // fast interrupt address design/lsu/el2_lsu.sv:63:- output logic [1:0] lsu_fir_error, // Error during fast interrupt lookup design/lsu/el2_lsu.sv:64:- design/lsu/el2_lsu.sv:65:- output logic lsu_single_ecc_error_incr, // Increment the ecc counter design/lsu/el2_lsu.sv:66:- output el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu exception packet design/lsu/el2_lsu.sv:67:- output logic lsu_imprecise_error_load_any, // bus load imprecise error design/lsu/el2_lsu.sv:68:- output logic lsu_imprecise_error_store_any, // bus store imprecise error design/lsu/el2_lsu.sv:69:- output logic [31:0] lsu_imprecise_error_a