[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_mem.sv:22:-`include "el2_param.vh" design/el2_mem.sv:23:- ) design/el2_mem.sv:24:-( design/el2_mem.sv:25:- input logic clk, design/el2_mem.sv:26:- input logic rst_l, design/el2_mem.sv:27:- input logic dccm_clk_override, design/el2_mem.sv:28:- input logic icm_clk_override, design/el2_mem.sv:29:- input logic dec_tlu_core_ecc_disable, design/el2_mem.sv:30:- design/el2_mem.sv:31:- //DCCM ports design/el2_mem.sv:32:- input logic dccm_wren, design/el2_mem.sv:33:- input logic dccm_rden, design/el2_mem.sv:34:- input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, design/el2_mem.sv:35:- input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, design/el2_mem.sv:36:- input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, design/el2_mem.sv:37:- input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, design/el2_mem.sv:38:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, design/el2_mem.sv:39:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, design/el2_mem.sv:40:- design/el2_mem.sv:41:- design/el2_mem.sv:42:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, design/el2_mem.sv:43:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, design/el2_mem.sv:44:- design/el2_mem.sv:45:- //ICCM ports design/el2_mem.sv:46:- input logic [pt.ICCM_BITS-1:1] iccm_rw_addr, design/el2_mem.sv:47:- input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle design/el2_mem.sv:48:- input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle design/el2_mem.sv:49:- input logic iccm_wren, design/el2_mem.sv:50:- input logic iccm_rden, design/el2_mem.sv:51:- input logic [2:0] iccm_wr_size, design/el2_mem.sv:52:- input logic [77:0] iccm_wr_data, design/el2_mem.sv:53:- design/el2_mem.sv:54:- output logic [63:0] iccm_rd_data, design/el2_mem.sv:55:- output logic [77:0] iccm_rd_data_ecc, design/el2_mem.sv:56:- design/el2_mem.sv:57:- // Icache and Itag Ports design/el2_mem.sv:58:- design/el2_mem.sv:59:- input logic [31:1] ic_rw_addr, design/el2_mem.sv:60:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, design/el2_mem.sv:61:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en, design/el2_mem.sv:62:- input logic ic_rd_en, design/el2_mem.sv:63:- input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. design/el2_mem.sv:64:- input logic ic_sel_premux_data, // Premux data sel design/el2_mem.sv:65:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, design/el2_mem.sv:66:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, design/el2_mem.sv:67:- design/el2_mem.sv:68:- input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC design/el2_mem.sv:69:- input logic [70:0] ic_debug_wr_data, // Debug wr cache. design/el2_mem.sv:70:- output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC design/el2_mem.sv:71:- input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. design/el2_mem.sv:72:- input logic ic_debug_rd_en, // Icache debug rd design/el2_mem.sv:73:- input logic ic_debug_wr_en, // Icache debug wr design/el2_mem.sv:74:- input logic ic_debug_tag_array, // Debug tag array design/el2_mem.sv:75:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. design/el2_mem.sv:76:- design/el2_mem.sv:77:- output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC design/e

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_mem.sv:92:- logic active_clk; design/el2_mem.sv:93:- rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* ); design/el2_mem.sv:94:- design/el2_mem.sv:95:- el2_mem_if mem_export_local (); design/el2_mem.sv:96:- design/el2_mem.sv:97:- assign mem_export .clk = clk; design/el2_mem.sv:98:- assign mem_export_local.clk = clk; design/el2_mem.sv:99:- design/el2_mem.sv:100:- assign mem_export .iccm_clken = mem_export_local.iccm_clken; design/el2_mem.sv:101:- assign mem_export .iccm_wren_bank = mem_export_local.iccm_wren_bank; design/el2_mem.sv:102:- assign mem_export .iccm_addr_bank = mem_export_local.iccm_addr_bank; design/el2_mem.sv:103:- assign mem_export .iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data; design/el2_mem.sv:104:- assign mem_export_local.iccm_bank_dout = mem_export. iccm_bank_dout; design/el2_mem.sv:105:- design/el2_mem.sv:106:- assign mem_export .dccm_clken = mem_export_local.dccm_clken; design/el2_mem.sv:107:- assign mem_export .dccm_wren_bank = mem_export_local.dccm_wren_bank; design/el2_mem.sv:108:- assign mem_export .dccm_addr_bank = mem_export_local.dccm_addr_bank; design/el2_mem.sv:109:- assign mem_export .dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank; design/el2_mem.sv:110:- assign mem_export_local.dccm_bank_dout = mem_export .dccm_bank_dout; design/el2_mem.sv:111:- design/el2_mem.sv:112:- // DCCM Instantiation design/el2_mem.sv:113:- if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable design/el2_mem.sv:114:- el2_lsu_dccm_mem #(.pt(pt)) dccm ( design/el2_mem.sv:115:- .clk_override(dccm_clk_override), design/el2_mem.sv:116:- .dccm_mem_export(mem_export_local.veer_dccm), design/el2_mem.sv:117:- .* design/el2_mem.sv:118:- ); design/el2_mem.sv:119:- end else begin: Gen_dccm_disable design/el2_mem.sv:120:- assign dccm_rd_data_lo = '0; design/el2_mem.sv:121:- assign dccm_rd_data_hi = '0; design/el2_mem.sv:122:- end design/el2_mem.sv:123:- design/el2_mem.sv:124:-if ( pt.ICACHE_ENABLE ) begin: icache design/el2_mem.sv:125:- el2_ifu_ic_mem #(.pt(pt)) icm ( design/el2_mem.sv:126:- .clk_override(icm_clk_override), design/el2_mem.sv:91:+ logic active_clk; design/el2_mem.sv:92:+ rvoclkhdr active_cg ( design/el2_mem.sv:93:+ .en(1'b1), design/el2_mem.sv:94:+ .l1clk(active_clk),

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_mem.sv:128:- ); design/el2_mem.sv:129:-end design/el2_mem.sv:130:-else begin design/el2_mem.sv:131:- assign ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0; design/el2_mem.sv:132:- assign ic_tag_perr = '0 ; design/el2_mem.sv:133:- assign ic_rd_data = '0 ; design/el2_mem.sv:134:- assign ictag_debug_rd_data = '0 ; design/el2_mem.sv:135:-end // else: !if( pt.ICACHE_ENABLE ) design/el2_mem.sv:136:- design/el2_mem.sv:137:- design/el2_mem.sv:138:- design/el2_mem.sv:139:-if (pt.ICCM_ENABLE) begin : iccm design/el2_mem.sv:140:- el2_ifu_iccm_mem #(.pt(pt)) iccm (.*, design/el2_mem.sv:141:- .clk_override(icm_clk_override), design/el2_mem.sv:142:- .iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]), design/el2_mem.sv:143:- .iccm_rd_data(iccm_rd_data[63:0]), design/el2_mem.sv:144:- .iccm_mem_export(mem_export_local.veer_iccm) design/el2_mem.sv:145:- ); design/el2_mem.sv:146:-end design/el2_mem.sv:147:-else begin design/el2_mem.sv:148:- assign iccm_rd_data = '0 ; design/el2_mem.sv:149:- assign iccm_rd_data_ecc = '0 ; design/el2_mem.sv:150:-end design/el2_mem.sv:96:+ ); design/el2_mem.sv:97:+ design/el2_mem.sv:98:+ el2_mem_if mem_export_local (); design/el2_mem.sv:99:+ design/el2_mem.sv:100:+ assign mem_export.clk = clk; design/el2_mem.sv:101:+ assign mem_export_local.clk = clk; design/el2_mem.sv:102:+ design/el2_mem.sv:103:+ assign mem_export.iccm_clken = mem_export_local.iccm_clken; design/el2_mem.sv:104:+ assign mem_export.iccm_wren_bank = mem_export_local.iccm_wren_bank; design/el2_mem.sv:105:+ assign mem_export.iccm_addr_bank = mem_export_local.iccm_addr_bank; design/el2_mem.sv:106:+ assign mem_export.iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data; design/el2_mem.sv:107:+ assign mem_export_local.iccm_bank_dout = mem_export.iccm_bank_dout; design/el2_mem.sv:108:+ design/el2_mem.sv:109:+ assign mem_export.dccm_clken = mem_export_local.dccm_clken; design/el2_mem.sv:110:+ assign mem_export.dccm_wren_bank = mem_export_local.dccm_wren_bank; design/el2_mem.sv:111:+ assign mem_export.dccm_addr_bank = mem_export_local.dccm_addr_bank; design/el2_mem.sv:112:+ assign mem_export.dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank; design/el2_mem.sv:113:+ assign mem_export_local.dccm_bank_dout = mem_export.dccm_bank_dout; design/el2_mem.sv:114:+ design/el2_mem.sv:115:+ // DCCM Instantiation design/el2_mem.sv:116:+ if (pt.DCCM_ENABLE == 1) begin : Gen_dccm_enable design/el2_mem.sv:117:+ el2_lsu_dccm_mem #( design/el2_mem.sv:118:+ .pt(pt) design/el2_mem.sv:119:+ ) dccm ( design/el2_mem.sv:120:+ .clk_override(dccm_clk_override), design/el2_mem.sv:121:+ .dccm_mem_export(mem_export_local.veer_dccm), design/el2_mem.sv:122:+ .* design/el2_mem.sv:123:+ ); design/el2_mem.sv:124:+ end else begin : Gen_dccm_disable design/el2_mem.sv:125:+ assign dccm_rd_data_lo = '0; design/el2_mem.sv:126:+ assign dccm_rd_data_hi = '0; design/el2_mem.sv:127:+ end design/el2_mem.sv:128:+ design/el2_mem.sv:129:+ if (pt.ICACHE_ENABLE) begin : icache design/el2_mem.sv:130:+ el2_ifu_ic_mem #( design/el2_mem.sv:131:+ .pt(pt) design/el2_mem.sv:132:+ ) icm ( design/el2_mem.sv:133:+ .clk_override(icm_clk_override), design/el2_mem.sv:134:+ .* design/el2_mem.sv:135:+ ); design/el2_mem.sv:136:+ end else begin design/el2_mem.sv:137:+ assign ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0; design/el2_mem.sv:138:+ assign ic_tag_perr = '0 ; design/el2_mem.sv:139:+ assign ic_rd_data = '0 ; design/el2_mem.sv:140:+ assign ictag_debug_rd_data = '0 ; design/el2_mem.sv:141:+ end // else: !if( pt.ICACHE_ENABLE ) design/el2_mem.sv:142:+ design/el2_mem.sv:143:+ design/el2_mem.sv:144:+ design/el2_mem.sv:145:+ if (pt.ICCM_ENABLE) begin : iccm design/el2_mem.sv:146:+ el2_ifu_iccm_mem #( design/el2_mem.sv:147:+ .p

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:288:- // clk ratio signals design/el2_veer_wrapper.sv:289:- input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:290:- input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:291:- input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:292:- input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface design/el2_veer_wrapper.sv:293:- design/el2_veer_wrapper.sv:294:- // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not) design/el2_veer_wrapper.sv:295:- design/el2_veer_wrapper.sv:296:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, design/el2_veer_wrapper.sv:297:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, design/el2_veer_wrapper.sv:298:- design/el2_veer_wrapper.sv:299:- input logic timer_int, design/el2_veer_wrapper.sv:300:- input logic soft_int, design/el2_veer_wrapper.sv:301:- input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, design/el2_veer_wrapper.sv:302:- design/el2_veer_wrapper.sv:303:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc design/el2_veer_wrapper.sv:304:- output logic dec_tlu_perfcnt1, design/el2_veer_wrapper.sv:305:- output logic dec_tlu_perfcnt2, design/el2_veer_wrapper.sv:306:- output logic dec_tlu_perfcnt3, design/el2_veer_wrapper.sv:307:- design/el2_veer_wrapper.sv:308:- // ports added by the soc team design/el2_veer_wrapper.sv:309:- input logic jtag_tck, // JTAG clk design/el2_veer_wrapper.sv:310:- input logic jtag_tms, // JTAG TMS design/el2_veer_wrapper.sv:311:- input logic jtag_tdi, // JTAG tdi design/el2_veer_wrapper.sv:312:- input logic jtag_trst_n, // JTAG Reset design/el2_veer_wrapper.sv:313:- output logic jtag_tdo, // JTAG TDO design/el2_veer_wrapper.sv:314:- design/el2_veer_wrapper.sv:315:- input logic [31:4] core_id, design/el2_veer_wrapper.sv:316:- design/el2_veer_wrapper.sv:317:- // Memory Export Interface design/el2_veer_wrapper.sv:318:- el2_mem_if.veer_sram_src el2_mem_export, design/el2_veer_wrapper.sv:319:- design/el2_veer_wrapper.sv:320:- // external MPC halt/run interface design/el2_veer_wrapper.sv:321:- input logic mpc_debug_halt_req, // Async halt request design/el2_veer_wrapper.sv:322:- input logic mpc_debug_run_req, // Async run request design/el2_veer_wrapper.sv:323:- input logic mpc_reset_run_req, // Run/halt after reset design/el2_veer_wrapper.sv:324:- output logic mpc_debug_halt_ack, // Halt ack design/el2_veer_wrapper.sv:325:- output logic mpc_debug_run_ack, // Run ack design/el2_veer_wrapper.sv:326:- output logic debug_brkpt_status, // debug breakpoint design/el2_veer_wrapper.sv:327:- design/el2_veer_wrapper.sv:328:- input logic i_cpu_halt_req, // Async halt req to CPU design/el2_veer_wrapper.sv:329:- output logic o_cpu_halt_ack, // core response to halt design/el2_veer_wrapper.sv:330:- output logic o_cpu_halt_status, // 1'b1 indicates core is halted desig

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:495:- wire lsu_axi_awvalid; design/el2_veer_wrapper.sv:496:- wire lsu_axi_awready; design/el2_veer_wrapper.sv:497:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid; design/el2_veer_wrapper.sv:498:- wire [31:0] lsu_axi_awaddr; design/el2_veer_wrapper.sv:499:- wire [3:0] lsu_axi_awregion; design/el2_veer_wrapper.sv:500:- wire [7:0] lsu_axi_awlen; design/el2_veer_wrapper.sv:501:- wire [2:0] lsu_axi_awsize; design/el2_veer_wrapper.sv:502:- wire [1:0] lsu_axi_awburst; design/el2_veer_wrapper.sv:503:- wire lsu_axi_awlock; design/el2_veer_wrapper.sv:504:- wire [3:0] lsu_axi_awcache; design/el2_veer_wrapper.sv:505:- wire [2:0] lsu_axi_awprot; design/el2_veer_wrapper.sv:506:- wire [3:0] lsu_axi_awqos; design/el2_veer_wrapper.sv:507:- design/el2_veer_wrapper.sv:508:- wire lsu_axi_wvalid; design/el2_veer_wrapper.sv:509:- wire lsu_axi_wready; design/el2_veer_wrapper.sv:510:- wire [63:0] lsu_axi_wdata; design/el2_veer_wrapper.sv:511:- wire [7:0] lsu_axi_wstrb; design/el2_veer_wrapper.sv:512:- wire lsu_axi_wlast; design/el2_veer_wrapper.sv:513:- design/el2_veer_wrapper.sv:514:- wire lsu_axi_bvalid; design/el2_veer_wrapper.sv:515:- wire lsu_axi_bready; design/el2_veer_wrapper.sv:516:- wire [1:0] lsu_axi_bresp; design/el2_veer_wrapper.sv:517:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid; design/el2_veer_wrapper.sv:518:- design/el2_veer_wrapper.sv:519:- // AXI Read Channels design/el2_veer_wrapper.sv:520:- wire lsu_axi_arvalid; design/el2_veer_wrapper.sv:521:- wire lsu_axi_arready; design/el2_veer_wrapper.sv:522:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid; design/el2_veer_wrapper.sv:523:- wire [31:0] lsu_axi_araddr; design/el2_veer_wrapper.sv:524:- wire [3:0] lsu_axi_arregion; design/el2_veer_wrapper.sv:525:- wire [7:0] lsu_axi_arlen; design/el2_veer_wrapper.sv:526:- wire [2:0] lsu_axi_arsize; design/el2_veer_wrapper.sv:527:- wire [1:0] lsu_axi_arburst; design/el2_veer_wrapper.sv:528:- wire lsu_axi_arlock; design/el2_veer_wrapper.sv:529:- wire [3:0] lsu_axi_arcache; design/el2_veer_wrapper.sv:530:- wire [2:0] lsu_axi_arprot; design/el2_veer_wrapper.sv:531:- wire [3:0] lsu_axi_arqos; design/el2_veer_wrapper.sv:532:- design/el2_veer_wrapper.sv:533:- wire lsu_axi_rvalid; design/el2_veer_wrapper.sv:534:- wire lsu_axi_rready; design/el2_veer_wrapper.sv:535:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid; design/el2_veer_wrapper.sv:536:- wire [63:0] lsu_axi_rdata; design/el2_veer_wrapper.sv:537:- wire [1:0] lsu_axi_rresp; design/el2_veer_wrapper.sv:538:- wire lsu_axi_rlast; design/el2_veer_wrapper.sv:539:- design/el2_veer_wrapper.sv:540:- //-------------------------- IFU AXI signals-------------------------- design/el2_veer_wrapper.sv:541:- // AXI Write Channels design/el2_veer_wrapper.sv:542:- wire ifu_axi_awvalid; design/el2_veer_wrapper.sv:543:- wire ifu_axi_awready; design/el2_veer_wrapper.sv:544:- wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid; design/el2_veer_wrapper.sv:545:- wire [31:0] ifu_axi_awaddr; design/el2_veer_wrapper.sv:546:- wire [3:0] ifu_axi_awregion; des

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_iccm_mem.sv:26:-`include "el2_param.vh" design/ifu/el2_ifu_iccm_mem.sv:27:- )( design/ifu/el2_ifu_iccm_mem.sv:28:- input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/ifu/el2_ifu_iccm_mem.sv:29:- input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/ifu/el2_ifu_iccm_mem.sv:30:- input logic rst_l, // reset, active low design/ifu/el2_ifu_iccm_mem.sv:31:- input logic clk_override, // Override non-functional clock gating design/ifu/el2_ifu_iccm_mem.sv:32:- design/ifu/el2_ifu_iccm_mem.sv:33:- input logic iccm_wren, // ICCM write enable design/ifu/el2_ifu_iccm_mem.sv:34:- input logic iccm_rden, // ICCM read enable design/ifu/el2_ifu_iccm_mem.sv:35:- input logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address design/ifu/el2_ifu_iccm_mem.sv:36:- input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle design/ifu/el2_ifu_iccm_mem.sv:37:- input logic iccm_correction_state, // ICCM under a correction - This is needed to guard replacements when hit design/ifu/el2_ifu_iccm_mem.sv:38:- input logic [2:0] iccm_wr_size, // ICCM write size design/ifu/el2_ifu_iccm_mem.sv:39:- input logic [77:0] iccm_wr_data, // ICCM write data design/ifu/el2_ifu_iccm_mem.sv:40:- design/ifu/el2_ifu_iccm_mem.sv:41:- el2_mem_if.veer_iccm iccm_mem_export, // RAM repositioned in testbench and connected by this interface design/ifu/el2_ifu_iccm_mem.sv:42:- design/ifu/el2_ifu_iccm_mem.sv:43:- output logic [63:0] iccm_rd_data, // ICCM read data design/ifu/el2_ifu_iccm_mem.sv:44:- output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc design/ifu/el2_ifu_iccm_mem.sv:45:- input logic scan_mode // Scan mode control design/ifu/el2_ifu_iccm_mem.sv:26:+ `include "el2_param.vh" design/ifu/el2_ifu_iccm_mem.sv:27:+) ( design/ifu/el2_ifu_iccm_mem.sv:28:+ input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/ifu/el2_ifu_iccm_mem.sv:29:+ input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/ifu/el2_ifu_iccm_mem.sv:30:+ input logic rst_l, // reset, active low design/ifu/el2_ifu_iccm_mem.sv:31:+ input logic clk_override, // Override non-functional clock gating design/ifu/el2_ifu_iccm_mem.sv:32:+ design/ifu/el2_ifu_iccm_mem.sv:33:+ input logic iccm_wren, // ICCM write enable design/ifu/el2_ifu_iccm_mem.sv:34:+ input logic iccm_rden, // ICCM read enable design/ifu/el2_ifu_iccm_mem.sv:35:+ input logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address design/ifu/el2_ifu_iccm_mem.sv:36:+ input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle design/ifu/el2_ifu_iccm_mem.sv:37:+ input logic

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_iccm_mem.sv:128:- rvdff #(1) selred0 (.*, design/ifu/el2_ifu_iccm_mem.sv:129:- .clk(active_clk), design/ifu/el2_ifu_iccm_mem.sv:130:- .din(sel_red0[i]), design/ifu/el2_ifu_iccm_mem.sv:131:- .dout(sel_red0_q[i])); design/ifu/el2_ifu_iccm_mem.sv:128:+ rvdff #(1) selred0 ( design/ifu/el2_ifu_iccm_mem.sv:129:+ .*, design/ifu/el2_ifu_iccm_mem.sv:130:+ .clk (active_clk), design/ifu/el2_ifu_iccm_mem.sv:131:+ .din (sel_red0[i]), design/ifu/el2_ifu_iccm_mem.sv:132:+ .dout(sel_red0_q[i]) design/ifu/el2_ifu_iccm_mem.sv:133:+ );

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/lsu/el2_lsu_dccm_mem.sv:33:-`include "el2_param.vh" design/lsu/el2_lsu_dccm_mem.sv:34:- )( design/lsu/el2_lsu_dccm_mem.sv:35:- input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/lsu/el2_lsu_dccm_mem.sv:36:- input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/lsu/el2_lsu_dccm_mem.sv:37:- input logic rst_l, // reset, active low design/lsu/el2_lsu_dccm_mem.sv:38:- input logic clk_override, // Override non-functional clock gating design/lsu/el2_lsu_dccm_mem.sv:39:- design/lsu/el2_lsu_dccm_mem.sv:40:- input logic dccm_wren, // write enable design/lsu/el2_lsu_dccm_mem.sv:41:- input logic dccm_rden, // read enable design/lsu/el2_lsu_dccm_mem.sv:42:- input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, // write address design/lsu/el2_lsu_dccm_mem.sv:43:- input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, // write address design/lsu/el2_lsu_dccm_mem.sv:44:- input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, // read address design/lsu/el2_lsu_dccm_mem.sv:45:- input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access design/lsu/el2_lsu_dccm_mem.sv:46:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data design/lsu/el2_lsu_dccm_mem.sv:47:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data design/lsu/el2_lsu_dccm_mem.sv:48:- el2_mem_if.veer_dccm dccm_mem_export, // RAM repositioned in testbench and connected by this interface design/lsu/el2_lsu_dccm_mem.sv:49:- design/lsu/el2_lsu_dccm_mem.sv:50:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank design/lsu/el2_lsu_dccm_mem.sv:51:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank design/lsu/el2_lsu_dccm_mem.sv:52:- design/lsu/el2_lsu_dccm_mem.sv:53:- input logic scan_mode design/lsu/el2_lsu_dccm_mem.sv:33:+ `include "el2_param.vh" design/lsu/el2_lsu_dccm_mem.sv:34:+) ( design/lsu/el2_lsu_dccm_mem.sv:35:+ input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/lsu/el2_lsu_dccm_mem.sv:36:+ input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/lsu/el2_lsu_dccm_mem.sv:37:+ input logic rst_l, // reset, active low design/lsu/el2_lsu_dccm_mem.sv:38:+ input logic clk_override, // Override non-functional clock gating design/lsu/el2_lsu_dccm_mem.sv:39:+ design/lsu/el2_lsu_dccm_mem.sv:40:+ input logic dccm_wren, // write enable design/lsu/el2_lsu_dccm_mem.sv:41:+ input logic dccm_rden, // read enable design/lsu/el2_lsu_dccm_mem.sv:42:+ input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, // write address design/lsu/el2_lsu_dccm_mem.sv:43:+ input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, // write address design/lsu/el2_lsu_dccm_mem.sv:44:+ input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, // read address design/lsu/el2_lsu_dccm_mem.sv:45:+ input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access design/lsu/el2_lsu_dccm_mem.sv:46:+ input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data desig