Add LSU DCCM UVM testbench for Verilator #398
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ci.yml
on: pull_request
Matrix: Build-Verilator / Build Verilator
Build-Spike
/
Build Spike
10s
Matrix: Test-Verification / Verification tests
Matrix: Test-Regression / Regression tests
Test-Microarchitectural
/
Lint microarchitectural tests
23s
Test-UVM
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UVM tests
30s
Matrix: Test-Microarchitectural / Microarchitectural tests
Matrix: Test-RISCOF / Run RISCOF tests
Test-RISCV-DV
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Download Renode
17s
Test-RISCV-DV
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Build VeeR-ISS
59s
Matrix: Test-RISCV-DV / Generate code for tests
Matrix: Test-RISCV-DV / Run RISC-V DV tests
Publish-to-GH-Pages
/
Build and Main Deploy
0s
Annotations
2 errors and 4 warnings
Test-UVM / UVM tests
Process completed with exit code 1.
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VeeR-EL2 CI
Canceling since a higher priority waiting request for 'concurrency-group-chipsalliance/Cores-VeeR-EL2-publish' exists
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Test-RISCOF / Run RISCOF tests (branch)
The following actions uses node12 which is deprecated and will be forced to run on node16: nanzm/[email protected], actions/cache@v2, actions/checkout@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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Test-RISCOF / Run RISCOF tests (branch)
The `set-output` command is deprecated and will be disabled soon. Please upgrade to using Environment Files. For more information see: https://github.blog/changelog/2022-10-11-github-actions-deprecating-save-state-and-set-output-commands/
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Test-RISCOF / Run RISCOF tests (toggle)
The following actions uses node12 which is deprecated and will be forced to run on node16: nanzm/[email protected], actions/cache@v2, actions/checkout@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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Test-RISCOF / Run RISCOF tests (toggle)
The `set-output` command is deprecated and will be disabled soon. Please upgrade to using Environment Files. For more information see: https://github.blog/changelog/2022-10-11-github-actions-deprecating-save-state-and-set-output-commands/
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artifacts-riscv_arithmetic_basic_test-renode-pyflow
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artifacts-riscv_arithmetic_basic_test-renode-uvm
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artifacts-riscv_arithmetic_basic_test-spike-pyflow
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artifacts-riscv_arithmetic_basic_test-spike-uvm
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artifacts-riscv_arithmetic_basic_test-whisper-pyflow
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artifacts-riscv_arithmetic_basic_test-whisper-uvm
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artifacts-riscv_ebreak_debug_mode_test-renode-uvm
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artifacts-riscv_mmu_stress_test-renode-uvm
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coverage_report
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regression_tests_coverage_data
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renode
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riscof-report
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riscv-dv_coverage_data
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riscv-dv_generated_code_pyflow
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riscv-dv_generated_code_uvm
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uarch_tests_coverage_data
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uarch_tests_logs
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veer-iss
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verification_dashboard
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verification_tests_coverage_data
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