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Add LSU DCCM UVM testbench for Verilator #396

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Add LSU DCCM UVM testbench for Verilator

Add LSU DCCM UVM testbench for Verilator #396

Triggered via pull request November 8, 2023 17:58
@kbieganskikbieganski
opened #131
antmicro:verilator-uvm-testbench
Status Failure
Total duration 46s
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ci.yml

on: pull_request
Matrix: Build-Verilator / Build Verilator
Build-Spike  /  Build Spike
5s
Build-Spike / Build Spike
Matrix: Test-Verification / Verification tests
Waiting for pending jobs
Matrix: Test-Regression / Regression tests
Waiting for pending jobs
Test-Microarchitectural  /  Lint microarchitectural tests
Test-Microarchitectural / Lint microarchitectural tests
Test-UVM  /  UVM tests
Test-UVM / UVM tests
Matrix: Test-Microarchitectural / Microarchitectural tests
Waiting for pending jobs
Test-RISCV-DV  /  Generate configs
Test-RISCV-DV / Generate configs
Matrix: Test-RISCOF / Run RISCOF tests
Waiting for pending jobs
Test-RISCV-DV  /  Build VeeR-ISS
Test-RISCV-DV / Build VeeR-ISS
Test-RISCV-DV  /  Download Renode
Test-RISCV-DV / Download Renode
Matrix: Test-RISCV-DV / Generate code for tests
Waiting for pending jobs
Matrix: Test-RISCV-DV / Run RISC-V DV tests
Waiting for pending jobs
Report-Coverage  /  Coverage report
Report-Coverage / Coverage report
Publish-to-GH-Pages  /  Build and Main Deploy
Publish-to-GH-Pages / Build and Main Deploy
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Annotations

1 error
Build-Verilator / Build Verilator (uvm, antmicro/verilator-1, df36e9ca2597aebe4b92c72461d945745b36c3e0)
Process completed with exit code 1.