The Use of MyHDL

MyHDL

While MyHDL has some very useful features for aiding in, and the designing of gateware, we have decided not to use its Python to HDL conversion functionality for a number of reasons (Listed below). We will however, rely heavily on its ability to "wrap" HDL as well as its co-simulation functionality.

1. We hope to target specific FPGA architectures and their optimized logic with the low-level primitive and this means that we will need to implement the HDL in a very specific way.
2. We wish to maintain the ability to create a pure Verilog design and with the python wrapper Verilog primitives it is still possible to do this.
3. The way that MyHDL generates its HDL is in one flat file, void of a hierarchical structure makes hard to read and understand the code. While designers should ideally be abstracted away from this, there will sometimes be the need to examine the generated code.