reg-test

An implementation of resource-friendly custom register sets in Xilinx Zynq FPGA fabric which are accessed/modified using Partial Dynamic Reconfiguration in AXIOM Beta

Instructions

On your local machine:

1. Install Vivado 2020.2. Make sure this version of Vivado is in your PATH.
2. Clone this repository with "--recursive" option in git and change directory to it
3. Run $ ./build.sh , which builds the design using Vivado and produces necessary database files
   i.e. build/reg_slice_map.db and build/slice_lut_db_min.json
4. Copy over the full bitstream file build/reg_test.bin to the Zynq device

On the Zynq device (AXIOM Beta):

1. Clone this repository with "--recursive" option in git and change directory to it
2. Configure the FPGA with the full bitstream file, you may use scripts/xilinx-devcfg/devcfg.py like this:
   # python devcfg.py write reg_test.bin, which uploads the bitfile reg_test.bin using the PCAP interface
3. $ mkdir build and copy over build/reg_slice_map.db and build/slice_lut_db_min.json to this build directory from your local machine
4. $ cd scripts and you can use the main script to read/write register values in the FPGA:
   # ./reg.py REG_32_CONST 0 -r, will read the value from the REG_32_CONST named register instance and 0th register index (from [0-31])
   # ./reg.py REG_32_CONST 0 -w 0xdeadbeef, will write the value "0xdeadbeef" to the specified register

Scripts

• xilinx-devcfg/devcfg.py: Used to access the PCAP interface in Xilinx Zynq to read/write full/partial bitstreams
• gen_partial_bitstream.py: Generates partial bitstream from a full bitstream using the specified frame addresses
• gen_slice_lut_db.py: Generates a custom database file (i.e. scripts/slice_lut_db.json) from Project X-Ray's Zynq database for bitstream information
• loc2addr.py: Show frame addresses associated with a slice location (e.g. SLICE_X26Y114/A6LUT)
• bitmod_init.py: Tool to read/modify LUT INIT values in a Xilinx Zynq bitstream
• reg2addr.py: Show frame addresses that can configure a register instance (e.g. REG_32_CONST)
• gen_slice_lut_db_min.py: Generates a minimal database file (i.e. build/slice_lut_db_min.json) out of the master database file (i.e. scripts/slice_lut_db.json) as per the resources used by the design (after build)
• bit2bin.py: Reverse the endianness of a bit file to produce bin file
• reg.py: Main script to read/write register values from/to a register in the FPGA
  
  

For more details, please refer to my final project report (submitted to my university for graduation on 15/05/2021) here: https://drive.google.com/file/d/1M6ZfTNf18en3QO0V77vp02iDad84V1jI/view?usp=sharing