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Idiv lzc opt #621

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Idiv lzc opt #621

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1e6f039
Idiv lzc optimization initial changes
kaamakshee Dec 16, 2022
7a8b5a0
Fixing signed/unsigned
dpetrisko Nov 14, 2022
07be79b
div_shift when divisor is zero
kaamakshee Dec 16, 2022
1a118e5
Initial restrictions
kaamakshee Dec 16, 2022
ea6bdb1
Merge branch 'bespoke-silicon-group:master' into idiv_lzc_opt
kaamakshee Dec 19, 2022
e487a1a
Code cleanup & Makefile flow for signed testing
kaamakshee Dec 19, 2022
4135852
Merge branch 'idiv_lzc_opt' of https://github.com/kaamakshee/basejump…
kaamakshee Dec 19, 2022
0f38a77
Moving div_shift calculation to datapath and passing it to the contro…
kaamakshee Dec 20, 2022
bcebf08
Eliminating the 4th mux input
kaamakshee Dec 20, 2022
6a8dd8f
Fixed mux input count
kaamakshee Feb 28, 2023
96ee5c1
Bits_per_iter=2 case updates
kaamakshee Mar 16, 2023
de05859
Merge branch 'idiv_lzc_opt' of https://github.com/kaamakshee/basejump…
kaamakshee Mar 16, 2023
d26fba3
naming convention fixes
kaamakshee Mar 16, 2023
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41 changes: 33 additions & 8 deletions bsg_misc/bsg_idiv_iterative.v
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Expand Up @@ -73,9 +73,28 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
,.clk_i(clk_i)
);

logic [`BSG_SAFE_CLOG2(width_p)-1:0] clz_c_result, clz_a_result;

bsg_counting_leading_zeros #(
.width_p(width_p)
) clz_c (
.a_i(dividend_i)
,.num_zero_o(clz_c_result)
);

bsg_counting_leading_zeros #(
.width_p(width_p)
) clz_a (
.a_i(divisor_i)
,.num_zero_o(clz_a_result)
);

//if the divisor is zero
wire zero_divisor_li = ~(| opA_r);

wire [`BSG_SAFE_CLOG2(width_p)-1:0] div_shift;
assign div_shift = zero_divisor_li ? width_p-1 : clz_a_result - clz_c_result;

wire [1:0] opA_sel_lo;
wire [width_p:0] opA_mux;

Expand All @@ -88,7 +107,8 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame

wire [width_p:0] opB_mux, opC_mux;
wire [bits_per_iter_p + 1:0] opB_sel_lo, opC_sel_lo;

wire [`BSG_WIDTH(width_p):0] shift_val;

if (bits_per_iter_p == 2) begin

bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB
Expand All @@ -105,20 +125,20 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame

end else begin

bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxB
(.data_i( {opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} )
bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB
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(.data_i( {opC_r, add1_out, {(add1_out << (width_p-shift_val+1)) | opC_r >> shift_val}} )
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,.data_o( opB_mux )
,.sel_one_hot_i(opB_sel_lo)
);

bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxC
(.data_i( {{dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}} )
bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC
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(.data_i( {{dividend_msb, dividend_i},add1_out, {(opC_r << (width_p-shift_val+1)) | ((~add1_out >> width_p) << (width_p-shift_val))}} )
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,.data_o( opC_mux )
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,.sel_one_hot_i(opC_sel_lo)
);
,.sel_one_hot_i(opC_sel_lo)
);

end

wire opA_ld_lo;
bsg_dff_en#(.width_p(width_p+1)) opA_reg
(.data_i (opA_mux)
Expand Down Expand Up @@ -240,6 +260,8 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
,.opA_is_neg_i (opA_r[width_p])
,.opC_is_neg_i (opC_r[width_p])

,.div_shift (div_shift)

,.opA_sel_o (opA_sel_lo)
,.opA_ld_o (opA_ld_lo)
,.opA_inv_o (opA_inv_lo)
Expand All @@ -256,7 +278,10 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
,.latch_signed_div_o (latch_signed_div_lo)
,.adder1_cin_o (adder1_cin_lo)

,.shift_val (shift_val)

,.v_o(v_o)
,.yumi_i(yumi_i)
);

endmodule // divide
14 changes: 11 additions & 3 deletions bsg_misc/bsg_idiv_iterative_controller.v
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Expand Up @@ -22,6 +22,8 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_
,input opA_is_neg_i
,input opC_is_neg_i

,input [`BSG_SAFE_CLOG2(width_p)-1:0] div_shift
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nit; coding convention is div_shift_i


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Add link to Google design doc in header comment

,output logic [1:0] opA_sel_o
,output logic opA_ld_o
,output logic opA_inv_o
Expand All @@ -38,6 +40,8 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_
,output logic latch_signed_div_o
,output logic adder1_cin_o

,output logic [`BSG_WIDTH(width_p):0] shift_val
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nit; coding convention is shift_val_o

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The max value of this seems to be 'BSG_WIDTH(width_p) as it's assigned to width_p or div_shift (which has max value of width_p). I think this port is 1b too wide (or am I misreading?)


,output logic v_o
,input yumi_i
);
Expand All @@ -46,7 +50,7 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_
logic r_neg_r;
logic neg_ld;
logic add1_neg_last_r, add2_neg_last_r;

typedef enum logic[5:0]
{WAIT, NEG0, NEG1, SHIFT,
CALC,
Expand All @@ -67,9 +71,13 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_
end
end

wire [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cyc;
assign calc_cyc = ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p/bits_per_iter_p;
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assign shift_val = (state == SHIFT) && ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p;

logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt;
wire calc_up_li = (state == CALC) && (calc_cnt < width_p/bits_per_iter_p);
wire calc_done = (calc_cnt == width_p/bits_per_iter_p);
wire calc_up_li = (state == CALC) && (calc_cnt < calc_cyc);
wire calc_done = (calc_cnt == calc_cyc);
bsg_counter_clear_up#(.max_val_p(width_p/bits_per_iter_p)
,.init_val_p(0)
,.disable_overflow_warning_p(1)) calc_counter
Expand Down
23 changes: 18 additions & 5 deletions testing/bsg_misc/bsg_idiv_iterative/Makefile
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@@ -1,16 +1,19 @@
# FIXME: set up VCS, should modified for different users.
include ../../../../bsg_cadenv/cadenv.mk
export BASEJUMP_STL_DIR=$(abspath ../../..)
INCDIR = +incdir+$(BASEJUMP_STL_DIR)/bsg_misc

PLI_OPTS = -P mypli.tab get_stim.c +acc
VCS_OP += +vcs+vcdpluson -debug_access+all
VCS_DEFINES =
CC = gcc
CFLAGS = -g
SRC=unsigned.c
SRC1=signed.c

ifdef SIGN
VCS_DEFINES += +define+SIGN=$(SIGN)
endif
ifdef UNSIGN
VCS_DEFINES += +define+UNSIGN=$(UNSIGN)
endif
ifdef WIDTH
VCS_DEFINES += +define+WIDTH=$(WIDTH)
endif
Expand All @@ -22,13 +25,23 @@ VCS_DEFINES += +define+ITERS=$(ITERS)
endif

vcs:
$(VCS) -full64 -sverilog $(VCS_OP) -Mupdate -f divide.files $(LIB_OPTS) $(PLI_OPTS) $(VCS_DEFINES)
$(VCS) -full64 -sverilog $(VCS_OP) -Mupdate -f sv.include -f divide.files $(LIB_OPTS) $(PLI_OPTS) $(VCS_DEFINES)
#./simv +vcs+stop+232100
./simv

xvcs:
$(VCS) -full64 -sverilog -Mupdate -RI -line -f divide.files $(LIB_OPTS) $(PLI_OPTS)

test: $(SRC)
$(CC) -o unsigned.o -c $^ $(CFLAGS) -lm -std=c99 -D ITERS=$(ITERS) -D WIDTH=$(WIDTH)
$(CC) unsigned.o -o test
./test

test1: $(SRC1)
$(CC) -o signed.o -c $^ $(CFLAGS) -lm -std=c99 -D ITERS=$(ITERS) -D WIDTH=$(WIDTH)
$(CC) signed.o -o test1
./test1

clean:
$(RM) -r csrc simv.daidir vcs.key simv ucli.key vcdplus.vpd s_output.txt u_output.txt u.txt s.txt
dve64:
Expand All @@ -38,4 +51,4 @@ gtk:
gtkwave vcd
verify:
egrep [0-9] u_expected.txt | diff -w u_output.txt -
egrep [0-9] s_expected.txt | diff -w s_output.txt -
# egrep [0-9] s_expected.txt | diff -w s_output.txt -
1 change: 0 additions & 1 deletion testing/bsg_misc/bsg_idiv_iterative/README.md
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@@ -1,7 +1,6 @@
Testbench:

- Set design parameters for design like bits/iteration and design width in the make command
UNSIGN - Test unsigned (default don't test)
SIGN - Test signed (default don't test)
WIDTH - design width
BITS_PER_ITER - 1 or 2 bits per iteration generated (different hardware designs)
Expand Down
4 changes: 4 additions & 0 deletions testing/bsg_misc/bsg_idiv_iterative/signed.c
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Expand Up @@ -3,8 +3,12 @@
// RISC-V ISA Manual: Section 7.2 - Division Operations
#include <stdio.h>
#include <math.h>
#ifndef WIDTH
#define WIDTH 4
#endif
#ifndef ITERS
#define ITERS 1 << (WIDTH * 2)
#endif
// #define ITERS 10000

// Function to compute quotient
Expand Down
5 changes: 5 additions & 0 deletions testing/bsg_misc/bsg_idiv_iterative/sv.include
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@@ -0,0 +1,5 @@
$BASEJUMP_STL_DIR/bsg_misc/bsg_counting_leading_zeros.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v
4 changes: 1 addition & 3 deletions testing/bsg_misc/bsg_idiv_iterative/test_bsg.v
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Expand Up @@ -95,10 +95,8 @@ module test_bsg;
$fwrite(f1,"%d %d %d %d\n", s_dividend, s_divisor, s_quotient, s_remainder);
$fwrite(f3,"%d %d\n", s_dividend, s_divisor);

`endif

// do the unsigned case
`ifdef UNSIGN
`else
u_dividend = dividend;
u_divisor = divisor;

Expand Down
6 changes: 5 additions & 1 deletion testing/bsg_misc/bsg_idiv_iterative/unsigned.c
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@@ -1,12 +1,16 @@
// Program to produce a file with the expected output
//jl Program to produce a file with the expected output
// for all possible inputs to an unsigned 4-bit divider pursuant to
// RISC-V ISA Manual: Section 7.2 - Division Operations

#include <stdio.h>
#include <math.h>
#include <limits.h>
#ifndef WIDTH
#define WIDTH 4
#endif
#ifndef ITERS
#define ITERS 1 << (WIDTH*2)
#endif
// #define ITERS 10000

// Function to compute quotient
Expand Down