Idiv lzc opt

bsg_misc/bsg_idiv_iterative.v

@@ -45,6 +45,7 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
     ,input                  yumi_i
     );
 
+
    // synopsys translate_off
    initial begin
         assert (bits_per_iter_p == 1 || bits_per_iter_p == 2)
@@ -72,6 +73,7 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
        ,.en_i   (latch_signed_div_lo)
        ,.clk_i(clk_i)
         );
+
 
    //if the divisor is zero
    wire         zero_divisor_li   =  ~(| opA_r);
@@ -87,7 +89,12 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
      );
 
    wire [width_p:0]  opB_mux, opC_mux;
-   wire [bits_per_iter_p + 1:0] opB_sel_lo, opC_sel_lo;
+   wire [3:0] opB_sel_lo, opC_sel_lo;
+
+
+   wire [$clog2(width_p)-1:0] div_shift;
+
+   let mask(value, select, lsb) = ((2**select-1) & (value >> lsb));
 
    if (bits_per_iter_p == 2) begin
 
@@ -105,20 +112,20 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
 
    end else begin
 
-      bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxB
-        (.data_i( {opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} )
+      bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB
+        (.data_i( {{mask(add1_out, div_shift+1, 0) << (width_p-div_shift) | mask(opC_r, width_p-div_shift, div_shift)}, opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} )
         ,.data_o( opB_mux )
         ,.sel_one_hot_i(opB_sel_lo)
         );
 
-      bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxC
-        (.data_i( {{dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}} )
+      bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC
+        (.data_i( {{(mask(opC_r, div_shift, 0) << (1+width_p-div_shift)) | (1<<width_p-div_shift)}, {dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}} )
         ,.data_o( opC_mux )
-	      ,.sel_one_hot_i(opC_sel_lo)
-	      );
+	,.sel_one_hot_i(opC_sel_lo)
+	);
 
   end
-   
+
    wire opA_ld_lo;
    bsg_dff_en#(.width_p(width_p+1)) opA_reg
        (.data_i (opA_mux)
@@ -149,6 +156,7 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
   wire        opA_clr_lo;
   wire        opB_clr_lo;
 
+
   wire [width_p:0] add1_in0;
   wire [width_p:0] add1_in1;  
   wire [width_p:0] add2_in0;
@@ -240,6 +248,9 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
       ,.opA_is_neg_i             (opA_r[width_p])
       ,.opC_is_neg_i             (opC_r[width_p])
 
+      ,.dividend_i                (dividend_i)
+      ,.divisor_i                (divisor_i)
+
       ,.opA_sel_o                (opA_sel_lo)
       ,.opA_ld_o                 (opA_ld_lo)
       ,.opA_inv_o                (opA_inv_lo)
@@ -255,6 +266,8 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame
 
       ,.latch_signed_div_o       (latch_signed_div_lo)
       ,.adder1_cin_o             (adder1_cin_lo)
+
+      ,.div_shift                (div_shift)
 
       ,.v_o(v_o)
       ,.yumi_i(yumi_i)

bsg_misc/bsg_idiv_iterative_controller.v

@@ -22,22 +22,28 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_
       ,input               opA_is_neg_i
       ,input               opC_is_neg_i
 
+
+      ,input [width_p-1: 0]   dividend_i
+      ,input [width_p-1: 0]   divisor_i
+
       ,output logic [1:0]  opA_sel_o
       ,output logic        opA_ld_o
       ,output logic        opA_inv_o
       ,output logic        opA_clr_l_o
 
-      ,output logic [bits_per_iter_p + 1:0]  opB_sel_o
+      ,output logic [3:0]  opB_sel_o
       ,output logic        opB_ld_o
       ,output logic        opB_inv_o
       ,output logic        opB_clr_l_o
 
-      ,output logic [bits_per_iter_p + 1:0]  opC_sel_o
+      ,output logic [3:0]  opC_sel_o
       ,output logic        opC_ld_o
 
       ,output logic        latch_signed_div_o
       ,output logic        adder1_cin_o
 
+      ,output [$clog2(width_p)-1:0] div_shift
+
       ,output logic        v_o
       ,input               yumi_i
       );
@@ -46,6 +52,11 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_
    logic r_neg_r;
    logic neg_ld;
    logic add1_neg_last_r, add2_neg_last_r;
+
+
+   logic [width_p-1:0] clz_dividend_input, clz_divisor_input;
+   logic [$clog2(width_p)-1:0] clz_c_result, clz_a_result;
+   //wire [$clog2(width_p)-1:0] div_shift;
 
    typedef enum logic[5:0] 
            {WAIT, NEG0, NEG1, SHIFT,
@@ -67,9 +78,29 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_
       end 
    end
 
+
+   assign clz_dividend_input = dividend_i;
+   assign clz_divisor_input  = divisor_i;
+
+   bsg_counting_leading_zeros #(
+     .width_p(width_p)
+     ) clz_c (
+       .a_i(clz_dividend_input)
+       ,.num_zero_o(clz_c_result)
+   );
+
+    bsg_counting_leading_zeros #(
+      .width_p(width_p)
+      ) clz_a (
+        .a_i(clz_divisor_input) 
+        ,.num_zero_o(clz_a_result)
+    );
+
+  assign div_shift = (zero_divisor_i) ? width_p-1 : clz_a_result - clz_c_result;
+
   logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt;
-  wire calc_up_li = (state == CALC) && (calc_cnt < width_p/bits_per_iter_p);
-  wire calc_done  = (calc_cnt == width_p/bits_per_iter_p);
+  wire calc_up_li = (state == CALC) && (calc_cnt < div_shift);
+  wire calc_done  = (calc_cnt == div_shift);
   bsg_counter_clear_up#(.max_val_p(width_p/bits_per_iter_p)
                        ,.init_val_p(0)
                        ,.disable_overflow_warning_p(1)) calc_counter
@@ -181,8 +212,8 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_
 	 opC_sel_o = 4'b0010;
          opB_sel_o = 4'b0010;
        end else begin
-	 opC_sel_o = 3'b001;
-         opB_sel_o = 3'b001;
+	 opC_sel_o = 4'b1000;
+         opB_sel_o = 4'b1000;
        end
     end
 

testing/bsg_misc/bsg_idiv_iterative/Makefile

@@ -1,16 +1,19 @@
 # FIXME:  set up VCS, should modified for different users.
 include ../../../../bsg_cadenv/cadenv.mk
+export BASEJUMP_STL_DIR=$(abspath ../../..)
+INCDIR = +incdir+$(BASEJUMP_STL_DIR)/bsg_misc
 
 PLI_OPTS = -P mypli.tab get_stim.c +acc
 VCS_OP     +=  +vcs+vcdpluson -debug_access+all
 VCS_DEFINES =
+CC = gcc
+CFLAGS = -g
+SRC=unsigned.c
+OUT=unsigned.o
 
 ifdef SIGN
 VCS_DEFINES += +define+SIGN=$(SIGN)
 endif
-ifdef UNSIGN
-VCS_DEFINES += +define+UNSIGN=$(UNSIGN)
-endif
 ifdef WIDTH
 VCS_DEFINES += +define+WIDTH=$(WIDTH)
 endif
@@ -22,13 +25,18 @@ VCS_DEFINES += +define+ITERS=$(ITERS)
 endif
 
 vcs:	
-	$(VCS) -full64 -sverilog $(VCS_OP)  -Mupdate -f divide.files $(LIB_OPTS) $(PLI_OPTS) $(VCS_DEFINES)
+	$(VCS) -full64 -sverilog $(VCS_OP)  -Mupdate -f sv.include -f divide.files $(LIB_OPTS) $(PLI_OPTS) $(VCS_DEFINES)
 	#./simv +vcs+stop+232100
 	./simv
 
 xvcs:
 	$(VCS) -full64 -sverilog -Mupdate -RI -line -f divide.files $(LIB_OPTS) $(PLI_OPTS)
 
+test: $(SRC)
+	$(CC) -o unsigned.o -c $^ $(CFLAGS) -lm -std=c99 -D ITERS=$(ITERS)
+	$(CC) unsigned.o -o test
+	./test
+
 clean:
 	$(RM) -r csrc simv.daidir vcs.key simv  ucli.key  vcdplus.vpd s_output.txt u_output.txt u.txt s.txt
 dve64:
@@ -38,4 +46,4 @@ gtk:
 	gtkwave vcd
 verify:
 	egrep [0-9] u_expected.txt | diff -w u_output.txt -
-	egrep [0-9] s_expected.txt | diff -w s_output.txt -
+#	egrep [0-9] s_expected.txt | diff -w s_output.txt -

testing/bsg_misc/bsg_idiv_iterative/README.md

@@ -1,7 +1,6 @@
 Testbench:
 
 - Set design parameters for design like bits/iteration and design width in the make command
-UNSIGN - Test unsigned (default don't test)
 SIGN - Test signed (default don't test)
 WIDTH - design width
 BITS_PER_ITER - 1 or 2 bits per iteration generated (different hardware designs)

testing/bsg_misc/bsg_idiv_iterative/sv.include

@@ -0,0 +1,5 @@
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counting_leading_zeros.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v

testing/bsg_misc/bsg_idiv_iterative/test_bsg.v

@@ -95,10 +95,8 @@ module test_bsg;
 	 $fwrite(f1,"%d %d %d %d\n", s_dividend, s_divisor, s_quotient, s_remainder);
          $fwrite(f3,"%d %d\n", s_dividend, s_divisor);
 
-	`endif
-
 	 // do the unsigned case
-	`ifdef UNSIGN
+     `else
 	 u_dividend = dividend;
 	 u_divisor  = divisor;
 

testing/bsg_misc/bsg_idiv_iterative/unsigned.c

@@ -1,12 +1,16 @@
-// Program to produce a file with the expected output
+//jl Program to produce a file with the expected output
 // for all possible inputs to an unsigned 4-bit divider pursuant to
 // RISC-V ISA Manual: Section 7.2 - Division Operations
 
 #include <stdio.h>
 #include <math.h>
 #include <limits.h>
+#ifndef WIDTH 
 #define WIDTH 4
+#endif
+#ifndef ITERS
 #define ITERS 1 << (WIDTH*2)
+#endif
 // #define ITERS 10000
 
 // Function to compute quotient