work on adsb example

bastibl · May 22, 2023 · 2afe6d6 · 2afe6d6
1 parent 5793937
commit 2afe6d6
Show file tree

Hide file tree

Showing 2 changed files with 19 additions and 24 deletions.
diff --git a/src/rtlsdr.rs b/src/rtlsdr.rs
@@ -133,8 +133,6 @@ impl RtlSdr {
         self.set_i2c_repeater(false)?;
         info!("Init complete");
 
-        self.set_sample_rate(2_000_000)?;
-        self.set_center_freq(100_000)?;
         Ok(())
     }
 
@@ -320,9 +318,12 @@ impl RtlSdr {
             .tuner
             .set_bandwidth(&self.handle, bw, r)?;
         self.set_i2c_repeater(false)?;
-        if inner.deref().borrow().tuner.get_info()?.id == TUNER_ID {
-            self.set_if_freq(inner.deref().borrow().tuner.get_if_freq()?)?;
-            self.set_center_freq(inner.deref().borrow().freq)?;
+        let is_tuner = inner.deref().borrow().tuner.get_info()?.id == TUNER_ID;
+        if is_tuner {
+            let if_freq = inner.deref().borrow().tuner.get_if_freq()?;
+            self.set_if_freq(if_freq)?;
+            let freq = inner.deref().borrow().freq;
+            self.set_center_freq(freq)?;
         }
         inner.deref().borrow_mut().bw = bw;
         Ok(())
@@ -492,7 +493,7 @@ impl RtlSdr {
         self.handle.demod_write_reg(1, 0x16, 0x00, 2)?;
 
         // info!("Clear DDC shift and IF registers");
-        for i in 0..5 {
+        for i in 0..6 {
             self.handle.demod_write_reg(1, 0x16 + i, 0x00, 1)?;
         }
         self.set_fir(DEFAULT_FIR)?;

diff --git a/src/tuners/r820t.rs b/src/tuners/r820t.rs
@@ -8,7 +8,7 @@ const R820T_I2C_ADDR: u16 = 0x34;
 // const R828D_I2C_ADDR: u8 = 0x74; for now only support the T
 const VER_NUM: u8 = 49;
 pub const R82XX_IF_FREQ: u32 = 3570000;
-const NUM_REGS: usize = 32;
+const NUM_REGS: usize = 35;
 const RW_REG_START: usize = 5; // registers 0-4 are read-only
 const NUM_CACHE_REGS: usize = NUM_REGS - RW_REG_START; // only cache RW regs
 const MAX_I2C_MSG_LEN: usize = 8;
@@ -22,6 +22,7 @@ const REG_INIT: [u8; NUM_CACHE_REGS] = [
     0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
     0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
     0x54, 0xae, 0x4a, 0xc0, /* 1c to 1f */
+    0x00, 0x00, 0x00,
 ];
 
 /* measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
@@ -401,15 +402,6 @@ impl Tuner for R820T {
 
                 // Set mixer gain
                 self.write_reg_mask(handle, 0x07, mix_index, 0x0f)?;
-
-                // LNA
-                self.write_reg_mask(handle, 0x05, 0, 0x10)?;
-
-                // Mixer
-                self.write_reg_mask(handle, 0x07, 0x10, 0x10)?;
-
-                // Set fixed VGA gain for now (26.5dB)
-                self.write_reg_mask(handle, 0x0c, 0x0b, 0x9f)?;
             }
         }
         Ok(())
@@ -472,12 +464,13 @@ impl Tuner for R820T {
             let mut lp_idx = 0;
             // Want the element before the first that is lower than bw
             for (i, freq) in R82XX_IF_LOW_PASS_BW_TABLE.iter().enumerate() {
+                lp_idx = i;
                 if bw > *freq {
                     break;
                 }
-                lp_idx = i;
             }
-            reg_0b |= 15 - lp_idx as u8;
+            lp_idx -= 1;
+            reg_0b |= (15 - lp_idx) as u8;
             real_bw += R82XX_IF_LOW_PASS_BW_TABLE[lp_idx];
 
             self.int_freq -= (real_bw / 2) as u32;
@@ -832,8 +825,8 @@ impl R820T {
             self.write_reg_mask(handle, 0x1e, lna_discharge, 0x1f)?;
             // agc clk 1Khz, external det1 cap 1u
             self.write_reg_mask(handle, 0x1a, 0x00, 0x30)?;
+            self.write_reg_mask(handle, 0x10, 0x00, 0x04)?;
         }
-        self.write_reg_mask(handle, 0x10, lna_discharge, 0x04)?;
         Ok(())
     }
 
@@ -883,7 +876,8 @@ impl R820T {
                 // Start trigger
                 self.write_reg_mask(handle, 0x0b, 0x10, 0x10)?;
                 // Stop trigger
-                self.write_reg_mask(handle, 0x0b, 0x00, 0x04)?;
+                self.write_reg_mask(handle, 0x0b, 0x00, 0x10)?;
+                self.write_reg_mask(handle, 0x0f, 0x00, 0x04)?;
 
                 // Check if calibration worked
                 let mut data: [u8; 5] = [0; 5];
@@ -892,10 +886,10 @@ impl R820T {
                 if self.fil_cal_code != 0x0f {
                     break;
                 }
-                // Narrowest
-                if self.fil_cal_code == 0x0f {
-                    self.fil_cal_code = 0;
-                }
+            }
+            // Narrowest
+            if self.fil_cal_code == 0x0f {
+                self.fil_cal_code = 0;
             }
         }
         self.write_reg_mask(handle, 0x0a, filt_q | self.fil_cal_code, 0x1f)?;