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[os] fix failing ethernet link on micro
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Silicon Errata Issues
Module 1:
Device fails to link after Asymmetric Pause capability is set
DESCRIPTION
Whenever the device's Asymmetric Pause capability (Register 4h, Bit [11]) is set to 1, link-up may fail after a link-up to
link-down transition (e.g., a cable disconnect).
END USER IMPLICATIONS
The device may fail to establish link when the Asymmetric Pause capability bit is set to 1.
Work around
Do not enable (set to 1) the Asymmetric Pause capability bit. If enabling this bit is required, a second link-up
attempt (e.g., disconnect and reconnect cable) is required to establish link.
PLAN
This erratum will not be corrected in a future revision.
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rroohhh committed Aug 25, 2020
1 parent 72304ce commit d3be200
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Showing 2 changed files with 2 additions and 9 deletions.
9 changes: 1 addition & 8 deletions boot/axiom-micro/devicetree.dts
Original file line number Diff line number Diff line change
Expand Up @@ -324,14 +324,7 @@
interrupt-parent = <&intc>;


phy-mode = "rgmii";
phy-handle = <&phy0>;

phy0: phy@0 {
// compatible = "ethernet-phy-id004d.d072", "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
reg = <0>;
};
phy-mode = "rgmii-id";
};

gem1: ethernet@e000c000 {
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2 changes: 1 addition & 1 deletion boot/kernel.config
Original file line number Diff line number Diff line change
Expand Up @@ -1800,7 +1800,7 @@ CONFIG_FIXED_PHY=y
# CONFIG_LXT_PHY is not set
CONFIG_MARVELL_PHY=y
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
CONFIG_MICREL_PHY=y
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
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