esp32,esp32s3: use mcuboot for qemu_openeth

[casaroli]

Summary

Update the esp32-devkitc:qemu_openeth and esp32s3-devkit:qemu_openeth configs to use MCUboot. Now, Espressif qemu supports MCUboot, so we can switch the app format.

Impact

• On esp32s3, the build was failing with the legacy app format because _ext_ram_bss_end and _ext_ram_bss_start are not defined in the "legacy" linker file.
• MCUboot is the new preferred way to build esp32/s3 binaries without needing to use custom partition table.

Testing

Now if we follow the instruction on the documentation, qemu works just fine.

Logs below are for esp-develop-9.0.0-20240606.

ESP32

./tools/configure.sh -l esp32-devkitc:qemu_openeth
make bootloader
make -j ESPTOOL_BINDIR=.
cat > efuse.hex <<EOF 
> 000000000000000000000000008000000000000000001000000000000000
000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
00000000
> EOF
xxd -r -p efuse.hex efuse.bin
../qemu/bin/qemu-system-xtensa -nographic -machine esp32 -m 4 \
    -nic user,model=open_eth \
    -drive file=nuttx.merged.bin,if=mtd,format=raw \
    -drive file=efuse.bin,if=none,format=raw,id=efuse \
    -global driver=nvram.esp32.efuse,property=drive,value=efuse

Output:

Adding SPI flash device
ets Jul 29 2019 12:21:46

rst:0x1 (POWERON_RESET),boot:0x12 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff7c98,len:6104
load:0x40078000,len:13172
load:0x40090000,len:7700
entry 0x4007b324
[esp32] [INF] *** Booting MCUboot build v1.10.0-131-gb206b99b ***
[esp32] [INF] [boot] chip revision: v3.0
[esp32] [INF] [boot.esp32] SPI Speed      : 40MHz
[esp32] [INF] [boot.esp32] SPI Mode       : DIO
[esp32] [INF] [boot.esp32] SPI Flash Size : 4MB
[esp32] [INF] [boot] Enabling RNG early entropy source...
[esp32] [INF] Primary image: magic=good, swap_type=0x1, copy_done=0x3, image_ok=0x1
[esp32] [INF] Scratch: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[esp32] [INF] Boot source: primary slot
[esp32] [INF] Image index: 0, Swap type: none
[esp32] [INF] Disabling RNG early entropy source...
[esp32] [INF] br_image_off = 0x10000
[esp32] [INF] ih_hdr_size = 0x20
[esp32] [INF] Loading image 0 - slot 0 from flash, area id: 1
[esp32] [INF] DRAM segment: start=0x12880, size=0x734, vaddr=0x3ffb6260
[esp32] [INF] IRAM segment: start=0x10040, size=0x2840, vaddr=0x40080000
[esp32] [INF] start=0x40081a0c
IROM segment aligned lma 0x00030000 vma 0x400d0000 len 0x01f0f8 (127224)
DROM segment aligned lma 0x00020000 vma 0x3f410000 len 0x003bdc (15324)

NuttShell (NSH) NuttX-12.8.0
nsh> 

ESP32-S3

./tools/configure.sh -l esp32s3-devkit:qemu_openeth
make bootloader
make -j ESPTOOL_BINDIR=.
../qemu/bin/qemu-system-xtensa -nographic -machine esp32s3 -m 4 \
    -nic user,model=open_eth \
    -drive file=nuttx.merged.bin,if=mtd,format=raw

Output:

Adding SPI flash device
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x4 (SPI_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:2
load:0x3fcd35a8,len:0x14d4
load:0x403b0000,len:0x1e14
load:0x403ba000,len:0x28c8
entry 0x403bc878
[esp32s3] [INF] *** Booting MCUboot build v1.10.0-131-gb206b99b ***
[esp32s3] [INF] [boot] chip revision: v0.3
[esp32s3] [INF] [boot.esp32s3] Boot SPI Speed : 40MHz
[esp32s3] [INF] [boot.esp32s3] SPI Mode       : DIO
[esp32s3] [INF] [boot.esp32s3] SPI Flash Size : 4MB
[esp32s3] [INF] [boot] Enabling RNG early entropy source...
[esp32s3] [INF] Primary image: magic=good, swap_type=0x1, copy_done=0x3, image_ok=0x1
[esp32s3] [INF] Scratch: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[esp32s3] [INF] Boot source: primary slot
[esp32s3] [INF] Image index: 0, Swap type: none
[esp32s3] [INF] Disabling RNG early entropy source...
[esp32s3] [INF] br_image_off = 0x10000
[esp32s3] [INF] ih_hdr_size = 0x20
[esp32s3] [INF] Loading image 0 - slot 0 from flash, area id: 1
[esp32s3] [INF] DRAM segment: start=0x12f94, size=0xeb0, vaddr=0x3fc8e490
[esp32s3] [INF] IRAM segment: start=0x10040, size=0x2f54, vaddr=0x40374000
[esp32s3] [INF] start=0x40374b80
IROM segment aligned lma 0x00020000 vma 0x42000000 len 0x01f667 (128615)
DROM segment aligned lma 0x00040000 vma 0x3c040000 len 0x003768 (14184)

NuttShell (NSH) NuttX-12.8.0
nsh>

Networking works as expected.

PR verification

• This PR introduces only one functional change.
• I have updated all required description fields above.
• My PR adheres to Contributing Guidelines and Documentation.
• My PR is ready for review and can be safely merged into a codebase.