xtensa/esp32: write encrypt func implementation

arch/xtensa/src/esp32/esp32_spiflash.c

@@ -281,6 +281,8 @@ static ssize_t esp32_bread_decrypt(struct mtd_dev_s *dev,
 #ifdef CONFIG_MTD_BYTE_WRITE
 static ssize_t esp32_write(struct mtd_dev_s *dev, off_t offset,
                            size_t nbytes, const uint8_t *buffer);
+static ssize_t esp32_write_encrypt(FAR struct mtd_dev_s *dev, off_t offset,
+                                   size_t nbytes, FAR const uint8_t *buffer);
 #endif
 static ssize_t esp32_bwrite(struct mtd_dev_s *dev, off_t startblock,
                             size_t nblocks, const uint8_t *buffer);
@@ -334,7 +336,7 @@ static struct esp32_spiflash_s g_esp32_spiflash1_encrypt =
             .read   = esp32_read_decrypt,
             .ioctl  = esp32_ioctl_encrypt,
 #ifdef CONFIG_MTD_BYTE_WRITE
-            .write  = NULL,
+            .write  = esp32_write_encrypt,
 #endif
             .name   = "esp32_mainflash_encrypt"
           },
@@ -1182,6 +1184,8 @@ static int IRAM_ATTR esp32_writedata_encrypted(
     {
       memcpy(tmp_buf, buffer, SPI_FLASH_ENCRYPT_UNIT_SIZE);
 
+      esp32_set_write_opt(priv);
+
       esp32_spiflash_opstart();
       esp_rom_spiflash_write_encrypted_enable();
 
@@ -2091,6 +2095,74 @@ static ssize_t esp32_write(struct mtd_dev_s *dev, off_t offset,
 
   return ret;
 }
+
+/****************************************************************************
+ * Name: esp32_write_encrypt
+ *
+ * Description:
+ *   write data to SPI Flash at designated address by SPI Flash hardware
+ *   encryption.
+ *
+ * Input Parameters:
+ *   dev    - ESP32 MTD device data
+ *   offset - target address offset
+ *   nbytes - data number
+ *   buffer - data buffer pointer
+ *
+ * Returned Value:
+ *   Writen bytes if success or a negative value if fail.
+ *
+ ****************************************************************************/
+
+static ssize_t esp32_write_encrypt(FAR struct mtd_dev_s *dev, off_t offset,
+                                   size_t nbytes, FAR const uint8_t *buffer)
+{
+  ssize_t ret;
+  struct esp32_spiflash_s *priv = MTD2PRIV(dev);
+
+  ASSERT(buffer);
+
+  if ((offset % SPI_FLASH_ENCRYPT_MIN_SIZE) ||
+    (nbytes % SPI_FLASH_ENCRYPT_MIN_SIZE))
+    {
+      return -EINVAL;
+    }
+
+#ifdef CONFIG_ESP32_SPIFLASH_DEBUG
+  finfo("esp32_write_encrypt(%p, 0x%x, %zu, %p)\n", dev, offset,
+        nbytes, buffer);
+#endif
+
+  /* Acquire the mutex. */
+
+  ret = nxmutex_lock(&g_lock);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+#ifdef CONFIG_ESP32_SPI_FLASH_SUPPORT_PSRAM_STACK
+  if (stack_is_psram())
+    {
+      ret = esp32_async_op(SPIFLASH_OP_CODE_ENCRYPT_WRITE, priv,
+                           offset, buffer, nbytes, 0);
+    }
+  else
+    {
+      ret = esp32_writeblk_encrypted(priv, offset, buffer, nbytes);
+    }
+#else
+  ret = esp32_writeblk_encrypted(priv, offset, buffer, nbytes);
+#endif
+
+  nxmutex_unlock(&g_lock);
+
+#ifdef CONFIG_ESP32_SPIFLASH_DEBUG
+  finfo("esp32_write_encrypt()=%d\n", ret);
+#endif
+
+  return ret;
+}
 #endif
 
 /****************************************************************************