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zynq-mpsoc: add support for ethernet #15720
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[Experimental Bot, please feedback here] Fill In The Commit Message: This PR contains a Commit with an Empty Commit Message. Please fill in the Commit Message with the PR Summary. The PR summary is okay, but could be improved by mentioning the specific Ethernet controller used (e.g., "Adds support for the Xilinx GEM Ethernet controller on the Zynq MPSOC"). The impact section needs significant improvement. Here's a breakdown:
The testing section is good, showing successful ping tests. However, more comprehensive testing is recommended. Consider including:
Revised Impact Section Example:
By addressing these points, you'll create a much stronger and more informative PR. Reviewers will appreciate the clarity and completeness, leading to a faster and smoother review process. |
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Please add commit log messages.
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choice | ||
prompt "ZYNQ Ethernet Interface" | ||
default ZYNQ_ENET4 |
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Why does ENET4 is default instead of ENET1?
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Because GMAC3 belong to PS of ZYNQ MPSOC, GMAC0~GMAC2 may depends on PL of ZYNQ MPSOC
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whats more, ZCU111 board use GMAC3
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config ZYNQ_GMAC_NRXBUFFERS | ||
int "Number of RX buffers" | ||
default 16 |
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Is there a upper limit for those 128 bytes blocks? If so, please include a range i.e. 1 to 32
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done! thanks for your review
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config ZYNQ_GMAC_NTXBUFFERS | ||
int "Number of TX buffers" | ||
default 8 |
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Ditto
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done
Zynq MPSOC The processing system (PS) is equipped with four gigabit Ethernet controllers.Each controller can be configured independently. Each controller uses a reduced gigabit media independent interface (RGMII) v2.0. This commit add support for ethernet of ZYNQ MPSOC.
The PS-side Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet interface, which connects to a TI DP83867IRPAP Ethernet RGMII PHY before being routed to an RJ45 Ethernet connector on ZCU111 board.The RGMII Ethernet PHY is boot strapped to PHY address 5'b01100 (0x0C) and Auto Negotiation is set to Enable.This commit add Ethernet support for ZCU111 board and TI DP83867IRPAP Ethernet RGMII PHY.
done! |
1. Changes the phyadd to 0xC to speed up the training of phyadd. 2. Set RX DMA buffer size configureable. 3. Create netnsh configs as ethernet boot from QSPI FLASH. 4. Fix some typo in apache#15720 which is nonsynchronous with local code.
Summary
Impact
Testing