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caliptra-rtl bbc9a32 Fix typo on logging plusarg check (#397)
antmicro · Jan 25, 2024 · f3ef71e · f3ef71e
1 parent cef0df6
commit f3ef71e
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/deps.json b/deps.json
@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "8ec0c6f18ec22c00de7538e7dccc648e7864aa9e"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "882fd9ff2c47e5fa761f19e05622c0200511080a"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "e52ab4363446f0504c1c122dbeb0321404e0f272"}]}
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "8ec0c6f18ec22c00de7538e7dccc648e7864aa9e"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "882fd9ff2c47e5fa761f19e05622c0200511080a"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "bbc9a329abb109abee5befc39419a5336672d036"}]}