Update revisions

Cores-VeeR-EL2 70563e50f2 Merge pull request #185 from antmicro/wsip/u_mode
42219183a5 Exclude whisper form riscv_full_interrupt_test
c11728fec8 Enable u mode in riscv-dv
bb6295bd98 Add pre-generated riscv-dv tests for user mode
16acd5f941 Add test for user mode
b7cc6dd5de Revert "Remove tests of unimplemented user mode"
632cf2ddfd Bump RISCV-DV

deps.json

@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "3937e484da24a09ae97820b2defe9a85fd7cea4e"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "6f0786210ff9079436b17ace5cd0cbd80b9d6c70"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "5ca1be7022f252bb369ae61f6db28b8556c03f03"}]}
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "3937e484da24a09ae97820b2defe9a85fd7cea4e"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "70563e50f2cc48be6697e0454eba1f2a6443b68c"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "5ca1be7022f252bb369ae61f6db28b8556c03f03"}]}