Update revisions

Cores-VeeR-EL2 1637d9751b0 verif: exu_alu: run format
fe82fbe3ee9 verif: exu_alu: udpate testbench to work with Python 3.9
10cd9e298bd verif: exu_alu: zer input signals
c6fcbcf652a verif: common.mk: update simulators options
204a58e5d5c Merge pull request #300 from chipsalliance/sideeffect
b16710b6ec8 design: el2_mem: connect mem_export.clk

deps.json

@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "8f4c75c5e43e61b994248307c814e01860303056"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "ca6557a9d7dc781f0485e01c16a8500bbf1efb33"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "de9d9c8685485bc5152ac81bd6ad42d6e167afe4"}]}
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "8f4c75c5e43e61b994248307c814e01860303056"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "1637d9751b03baa6615b8c97a2612fce2c3a9ea0"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "de9d9c8685485bc5152ac81bd6ad42d6e167afe4"}]}