Update revisions

Cores-VeeR-EL2 2af78bf0909 Merge pull request #303 from chipsalliance/cm-cfg
3b3844e0439 CI: generate data for coverview
c329ad92ad5 Set coverage off on core_id
6c435f962b7 axi memory: align address
5d419e14da6 Bump verilator
f129fb58459 CI: merge Verilator reports and pass them to custom step
9983c505137 openocd/gdb: gather more data
49805a54115 openocd/gdb test: update sim options
5883d7eccae cm.cfg drop axi_crossbar_wrap_2x1
64cff1ec75b sim_gdb: shorten sleep
d99fb40f60e gdb_test: chose proper sim binary and sim start string
9ff760c3661 test.gdb: drop failing memory accesses
692ed2eef86 gdb_test: set GCC_PREFIX is it is not set
5d7500c51aa CI: add custom openocd tests
5186e9e716e openocd_test: use diferent sim start strings for diferent binaries
edb22bf0b5a testbench: enable dmi core in all simulators
0596ebc143c utils.sh: use date for bash 4 compatibility
9d19ae34c60 openocd_test: detect the simulation binary wait for common simulation log line
67f9c3809e7 Makefile: add axi4_mux files to TBFILES
2ebf40d9479 testbench/axi4_mux: drop timescale
5bad8954ebb testbench/hex: add csr_msecfg
8d67bd8e1d0 CI: run custom regression test in matrix
a1e25c1cae2 testbench: add cpu halt test
91d5abd330d testbench: or reduce ME signal in IC_TAG macro
eb1d39fcd4a testbench: reconnect IC TAG mem
b12fba626eb tb_top: toggle reset signal
54ab41b7fc7 waive rst_vec and nmi_vec signals
1e00195a649 Add cm config

deps.json

@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "8f4c75c5e43e61b994248307c814e01860303056"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "067ca034e9a350b26459ade441cb5de12a37a7eb"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "de9d9c8685485bc5152ac81bd6ad42d6e167afe4"}]}
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "8f4c75c5e43e61b994248307c814e01860303056"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "2af78bf0909d08332326c5896cc4d65a05a97c3a"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "de9d9c8685485bc5152ac81bd6ad42d6e167afe4"}]}