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index #774

Triggered via schedule January 18, 2025 00:12
Status Failure
Total duration 24m 22s
Artifacts 1

index.yml

on: schedule
update-revisions
18m 0s
update-revisions
Matrix: index-cores
setup-default-service
21s
setup-default-service
Matrix: deploy-to-gcp
gcr-cleaner
0s
gcr-cleaner
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3 errors and 6 warnings
deploy-to-gcp (Cores-VeeR-EL2, https://github.com/chipsalliance/Cores-VeeR-EL2, main, 89b9c62af8a...
The job was canceled because "caliptra-rtl_https___gith" failed.
update-revisions
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636
setup-default-service
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636
index-cores (caliptra-rtl, https://github.com/chipsalliance/caliptra-rtl, main, 69bc3aa1f839efd16...: home/runner/work/_actions/antmicro/verible-indexing-action/v1.1.1/build.sh#L39
verible-verilog-kythe-extractor: E0118 00:30:53.451981 2050 verilog_kythe_extractor.cc:218] Encountered some issues while indexing files (could result in missing indexing data): E0118 00:30:53.452542 2050 verilog_kythe_extractor.cc:222] Unable to find 'uvm_macros.svh' among the included paths: src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/tests/src, src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src, src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src, src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src, src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src, src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src, src/keyvault/rtl, src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/tests/src, src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/sequences/src, src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_in_pkg/src, src/hmac/uvmf_2022/uvmf_template_output/verification_ip/interface_packages/HMAC_out_pkg/src, src/hmac/uvmf_2022/uvmf_template_output/verification_ip/environment_packages/HMAC_env_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/sha_accel, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/soc_ifc, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/cptra, src/soc_ifc/tb, src/soc_ifc/rtl, src/caliptra_prim/rtl, src/riscv_core/veer_el2/tb, src/riscv_core/veer_el2/rtl, src/riscv_core/veer_el2/rtl/include, src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/tests/src, src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/sequences/src, src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg/src, src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg/src, src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/environment_packages/ECC_env_pkg/src, src/sha512/uvmf_sha
index-cores (Cores-VeeR-EL2, https://github.com/chipsalliance/Cores-VeeR-EL2, main, 89b9c62af8a83...: home/runner/work/_actions/antmicro/verible-indexing-action/v1.1.1/build.sh#L39
verible-verilog-kythe-extractor: E0118 00:32:04.454035 2040 verilog_kythe_extractor.cc:218] Encountered some issues while indexing files (could result in missing indexing data): E0118 00:32:04.454063 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454064 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454065 2040 verilog_kythe_extractor.cc:222] Syntax error. E0118 00:32:04.454067 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454068 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454069 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_transaction_sequence_item.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454070 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_sequencer.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454071 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_sequence.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454072 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_driver.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454073 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_monitor.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454074 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_agent.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454075 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_scoreboard.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454076 2040 verilog_kythe_extractor.cc:222] Unable to find 'uvm_pkg.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454077 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_interface.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454078 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_base_test.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454079 2040 verilog_kythe_extractor.cc:222] Unable to find 'dccm_memtest.sv' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454081 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454082 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454083 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454084 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454085 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454086 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454087 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454088 2040 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: testbench, tools/riscv-dv, design/include, . E0118 00:32:04.454089 2040 verilog
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server-files
338 MB