Docs: Update gateware wording

Signed-off-by: Peter Katarzynski <[email protected]>
antmicro · Nov 29, 2024 · fe314b4 · fe314b4
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Showing 16 changed files with 11 additions and 237 deletions.
diff --git a/.gitignore b/.gitignore
@@ -13,3 +13,4 @@ sdram_init.py
 vivado.*
 riscv64-unknown-elf-gcc*
 docs/build
+docs/source/build/**
diff --git a/docs/source/arty.md b/docs/source/arty.md
@@ -11,7 +11,7 @@ Arty-A7 board
 
 The following instructions explain how to set up the board.
 
-For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/arty/documentation/index.rst).
+For FPGA digital design documentation for this board, refer to the [Digital design](build/arty/documentation/index.rst) chapter.
 
 ## Board configuration
 

diff --git a/docs/source/build/arty/documentation/index.rst b/docs/source/build/arty/documentation/index.rst
diff --git a/docs/source/build/ddr4_datacenter_test_board/documentation/index.rst b/docs/source/build/ddr4_datacenter_test_board/documentation/index.rst
diff --git a/docs/source/build/ddr5_test_board/documentation/index.rst b/docs/source/build/ddr5_test_board/documentation/index.rst
diff --git a/docs/source/build/ddr5_tester/documentation/index.rst b/docs/source/build/ddr5_tester/documentation/index.rst
diff --git a/docs/source/build/lpddr4_test_board/documentation/index.rst b/docs/source/build/lpddr4_test_board/documentation/index.rst
diff --git a/docs/source/build/zcu104/documentation/index.rst b/docs/source/build/zcu104/documentation/index.rst
diff --git a/docs/source/data_center_rdimm_ddr4_tester.md b/docs/source/data_center_rdimm_ddr4_tester.md
@@ -13,7 +13,7 @@ The hardware is open and can be found on GitHub:
 
 The following instructions explain how to set up the board.
 
-For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/ddr4_datacenter_test_board/documentation/index.rst).
+For FPGA digital design documentation for this board, refer to the [Digital design](build/ddr4_datacenter_test_board/documentation/index.rst) chapter.
 
 ## IO map
 

diff --git a/docs/source/data_center_rdimm_ddr5_tester.md b/docs/source/data_center_rdimm_ddr5_tester.md
@@ -9,7 +9,7 @@ The hardware is open and can be found on [GitHub](https://github.com/antmicro/rd
 
 The following instructions explain how to set up the board.
 
-For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/ddr5_test_board/documentation/index.rst).
+For FPGA digital design documentation for this board, refer to the [Digital design](build/ddr5_test_board/documentation/index.rst) chapter.
 
 ## IO map
 

diff --git a/docs/source/general.md b/docs/source/general.md
@@ -4,7 +4,7 @@ The aim of this project is to provide a platform for testing [DRAM vulnerability
 
 ## Architecture
 
-The setup consists of FPGA gateware and application side software.
+The setup consists of FPGA digital design and application side software.
 The following diagram illustrates the general system architecture.
 
 ```{image} ./images/architecture.png
@@ -102,7 +102,7 @@ Next time you want to use a bitstream packaged in such way, all you need to do i
 
 ## Local documentation build
 
-The gateware part of the documentation is auto-generated from source files.
+The digital design part of the documentation is auto-generated from source files.
 Other files are static and are located in the `doc/` directory.
 To build the documentation, enter:
 

diff --git a/docs/source/introduction.md b/docs/source/introduction.md
@@ -69,7 +69,7 @@ The application side consists of a set of Python scripts communicating with the
 * [Performing attacks (hammering)](hammering.md) - instructions for performing rowhammer attacks, examples, DRAM config guide and Python utility overview
 * [Result visualization](visualization.md) - instructions for generating plots and visualizations
 * [Test-writing playbook](playbook.md) - guide for using dedicated Python classes and scripts for writing rowhammer-related tests
-* Gateware documentation - FPGA gateware documented per-board:
+* Digital design- FPGA digital design documented per-board:
     * [Arty-A7 board](build/arty/documentation/index.rst)
     * [LPDDR4 Test Board](build/lpddr4_test_board/documentation/index.rst)
     * [Data Center RDIMM DDR4 Tester](build/ddr4_datacenter_test_board/documentation/index.rst)

diff --git a/docs/source/lpddr4_test_board.md b/docs/source/lpddr4_test_board.md
@@ -11,7 +11,7 @@ The hardware is open and can be found on GitHub:
 - Test board: <https://github.com/antmicro/lpddr4-test-board>
 - Testbed: <https://github.com/antmicro/lpddr4-testbed>
 
-For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/lpddr4_test_board/documentation/index.rst).
+For FPGA digital design documentation for this board, refer to the [Digital design](build/lpddr4_test_board/documentation/index.rst) chapter.
 
 ## IO map
 

diff --git a/docs/source/setup.md b/docs/source/setup.md
@@ -78,7 +78,7 @@ To use a bitstream packaged this way, run `unzip your-bitstream-file.zip`.
 
 ## Local documentation build
 
-The gateware part of the documentation is auto-generated from source files.
+The part of the documentation related to the ditital design is auto-generated from source files.
 Other files are static and are located in the `doc/` directory.
 To build the documentation, enter:
 

diff --git a/docs/source/so_dimm_ddr5_tester.md b/docs/source/so_dimm_ddr5_tester.md
@@ -11,7 +11,7 @@ The SO-DIMM DDR5 tester is an open source hardware test platform that enables te
 The hardware is open and can be found on GitHub:
 <https://github.com/antmicro/sodimm-ddr5-tester>
 
-For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/ddr5_tester/documentation/index.rst).
+For FPGA digital design documentation for this board, refer to the [Digital design](build/ddr5_tester/documentation/index.rst) chapter.
 
 ## IO map
 

diff --git a/docs/source/zcu104.md b/docs/source/zcu104.md
@@ -15,7 +15,7 @@ A simple EtherBone server is implemented for this purpose (the source code can b
 
 The following instructions show how to set up the board for the first time.
 
-For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/zcu104/documentation/index.rst).
+For FPGA design documentation for this board, refer to the [Digital design](build/zcu104/documentation/index.rst) chapter.
 
 ## Board configuration