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Issues list

IEEE Std 1800-2023(2017) deviation
#24 by iagrigorov was closed Jan 23, 2025
1
What is the function of locked_by_route_ff in vc_buffer?
#23 by Alexander-0619 was closed Dec 18, 2024
4
Does the router use a pipeline structure?
#21 by Alexander-0619 was closed Dec 18, 2024
8
question about test_irqs
#20 by sfyhhh was closed Dec 11, 2024
4
questions about regression test
#19 by sfyhhh was closed Sep 23, 2024
3
Regarding Head, Body and Tail Flits
#18 by kutaybulun was closed Aug 17, 2024
1
FPGA Implementation Multiple Driver Error
#17 by kutaybulun was closed Aug 14, 2024
4
Implementation on an FPGA
#16 by kutaybulun was closed Jul 25, 2024
1
How to use this repo
#15 by Rohit123451 was closed Dec 12, 2023
1
regarding the configurable files
#14 by Siddhanth09 was closed Dec 12, 2023
4
Design of flit fifo of RaveNoC Router using Block RAM for area optimization in FPGA platform
#10 by madhumita-mukherjee was closed Jan 17, 2023
14
router top file：Confused about ns_con
#9 by Elena32061 was closed Sep 13, 2022
2
what does *N-*FIFO mean here?
#8 by Elena32061 was closed Sep 13, 2022
3
Why is IRQ needed？
#7 by Elena32061 was closed Sep 10, 2022
2
Why the project only has axi slave interface
#6 by Elena32061 was closed Sep 10, 2022
1
What is the meaning of “ def_wr_dec, def_rd_dec ” in ”axi slave if“ file
#5 by Elena32061 was closed Sep 7, 2022
3
Unable to run regression tests
#4 by kevinpinto98 was closed Jul 7, 2022
7
What is the interpretation of names axi_mosi_if and axi_miso_if
#3 by hughperkins was closed May 10, 2022
2
Nit: missing a space in license paragraph
#2 by hughperkins was closed May 11, 2022
1
ProTip! Follow long discussions with comments:>50.