PhD student @HKUST(GZ)
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HKUST(GZ)
- Guangzhou
- https://zhiyuanyan.netlify.app/
- https://orcid.org/0000-0003-3857-6649
Popular repositories Loading
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RISCV-design
RISCV-design PublicSome RISCV cores based on Verilog design, for SQED detection
Verilog 8
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HW-Formal-Paper
HW-Formal-Paper PublicForked from fangwenji/HW-Formal-Paper
Recent papers related to hardware formal verification.
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ILAng
ILAng PublicForked from PrincetonUniversity/ILAng
A Modeling and Verification Platform for SoCs using ILAs
C++
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