USTC Computer Organization and Design Course Project Design RISC-V CPU by Verilog HDL, and complete implement on FPGA platform online
- Design of ALU and FLS
- Use Register Files to realize FIFO
- Program Fibonacci Numbers by using RISC-V assembly language
- Design Single Cycle RISC-V CPU which supports 10 instructions
- Design Multi Cycle RISC-V CPU (Five stage pipeline)
Finished by Zhichen Zeng, USTC, 2022.5