Recognizing declarations representing blocks of memory

[philiprbrenan]

In module Memory I declare the following arrays which I hoped would be recognized as declaring blocks of memory following https://yosyshq.readthedocs.io/projects/yosys/en/manual-rewrite/using_yosys/memory_mapping.html

  reg [DATA_BITS   -1:0] memory     [ARRAYS-1:0][ARRAY_LENGTH-1:0];             // Memory containing arrays in fixed blocks
  reg [DATA_BITS   -1:0] copy                   [ARRAY_LENGTH-1:0];             // Copy of one array
  reg [INDEX_BITS    :0] arraySizes [ARRAYS-1:0];                               // Current size of each array
  reg [ADDRESS_BITS-1:0] freedArrays[ARRAYS-1:0];                               // Currently freed arrays
  reg                    allocations[ARRAYS-1:0];                               // Currently allocated arrays

When I run:

 yosys -d -Q -p "read_verilog -nomem2reg verilog/fpga/tests/Push2/fpga.sv; synth_gowin -top fpga -json verilog/fpga/tests/Push2/fpga.json"

I get the message:

2.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$94a93e0a0f69389e40b8e6038fccab8ee3dca5c4\Memory.

as can be seen in the output of a github action:

https://github.com/philiprbrenan/zeroLowLevel/actions/runs/5570609972/jobs/10174831748

This message would seem to imply that the arrays have not been recognized as memory and have instead been converted into individual registers.

Please could you tell me how to make synth_gowin accept these arrays as blocks of memory?