Basic timing model

YosysHQ · Dec 26, 2024 · 352340b · 352340b
1 parent 150428f
commit 352340b
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Showing 5 changed files with 28 additions and 4 deletions.
diff --git a/himbaechel/uarch/gatemate/constids.inc b/himbaechel/uarch/gatemate/constids.inc
@@ -119,3 +119,5 @@ X(2D_IN)
 
 X(CC_BUFG)
 X(BUFG)
+
+X(CPE_DFF)
diff --git a/himbaechel/uarch/gatemate/extra_data.h b/himbaechel/uarch/gatemate/extra_data.h
@@ -32,8 +32,9 @@ NPNR_PACKED_STRUCT(struct GateMatePipExtraDataPOD {
     uint8_t type;
 });
 
-enum MuxFlags {
-    MUX_INVERT  = 1,
+enum MuxFlags
+{
+    MUX_INVERT = 1,
     MUX_VISIBLE = 2,
 };
 

diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc
@@ -59,9 +59,9 @@ bool GateMateImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
         Loc loc = ctx->getBelLocation(bel);
         int x = loc.x - 2;
         int y = loc.y - 2;
-        if (x<2 || x>167)
+        if (x < 2 || x > 167)
             return false;
-        if (y<2 || y>127)
+        if (y < 2 || y > 127)
             return false;
         return true;
     }

diff --git a/himbaechel/uarch/gatemate/gen/arch_gen.py b/himbaechel/uarch/gatemate/gen/arch_gen.py
@@ -61,6 +61,26 @@ def set_timings(ch):
     speed = "DEFAULT"
     tmg = ch.set_speed_grades([speed])
 
+    lut = ch.timing.add_cell_variant(speed, "CPE")
+    lut.add_comb_arc(f"IN1", "OUT1", TimingValue(455, 459))
+    lut.add_comb_arc(f"IN2", "OUT1", TimingValue(450, 457))
+    lut.add_comb_arc(f"IN3", "OUT1", TimingValue(427, 430))
+    lut.add_comb_arc(f"IN4", "OUT1", TimingValue(423, 424))
+    lut.add_comb_arc(f"IN5", "OUT1", TimingValue(416, 418))
+    lut.add_comb_arc(f"IN6", "OUT1", TimingValue(413, 422))
+    lut.add_comb_arc(f"IN7", "OUT1", TimingValue(372, 374))
+    lut.add_comb_arc(f"IN8", "OUT1", TimingValue(275, 385))
+
+    lut.add_comb_arc(f"IN1", "OUT2", TimingValue(479, 484))
+    lut.add_comb_arc(f"IN2", "OUT2", TimingValue(471, 488))
+    lut.add_comb_arc(f"IN3", "OUT2", TimingValue(446, 449))
+    lut.add_comb_arc(f"IN4", "OUT2", TimingValue(443, 453))
+
+    dff = ch.timing.add_cell_variant(speed, "CPE_DFF")
+    dff.add_setup_hold("CLK", "IN1", ClockEdge.RISING, TimingValue(60), TimingValue(50))
+    dff.add_clock_out("CLK", "OUT1", ClockEdge.RISING, TimingValue(60))
+    dff.add_clock_out("CLK", "OUT2", ClockEdge.RISING, TimingValue(60))
+
 def main():
     # Range needs to be +1, but we are adding +2 more to coordinates, since 
     # they are starting from -2 instead of zero required for nextpnr

diff --git a/himbaechel/uarch/gatemate/pack.cc b/himbaechel/uarch/gatemate/pack.cc
@@ -337,6 +337,7 @@ void GateMatePacker::pack_cpe()
         ci.params[id_S] = Property(0b11, 2);
         ci.params[id_CLK] = Property(0b10, 2);
         ci.params[id_FF_INIT] = Property(0b10, 2);
+        ci.timing_index = ctx->get_cell_timing_idx(id_CPE_DFF);
 
         ci.unsetParam(ctx->id("SR_VAL"));
         ci.unsetParam(ctx->id("SR_INV"));
Original file line number	Diff line number	Diff line change
Expand Up		@@ -119,3 +119,5 @@ X(2D_IN)

		X(CC_BUFG)
		X(BUFG)

		X(CPE_DFF)