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passing init tests.
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dkorolij committed Dec 11, 2024
1 parent 5d0462c commit e511fae
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Showing 7 changed files with 447 additions and 52 deletions.
52 changes: 28 additions & 24 deletions finn-rtllib/mvu/mv_matrix_load.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -99,26 +99,27 @@ module mv_matrix_load #(
// Consts and types
// ----------------------------------------------------------------------------

localparam int unsigned SF = MH/SIMD;
localparam int unsigned NF = MW/PE;
localparam int unsigned SF = MW/SIMD;
localparam int unsigned NF = MH/PE;

localparam integer SIMD_BITS = $clog2(SIMD);
localparam integer SIMD_BITS = (SIMD == 1) ? 1 : $clog2(SIMD);
localparam integer WGT_ADDR_BITS = $clog2(NF * SF);
localparam integer RAM_BITS = (ACTIVATION_WIDTH + 7)/8 * 8;
localparam integer WGT_EN_BITS = RAM_BITS / 8;
localparam integer NF_BITS = $clog2(NF);
localparam integer MH_BITS = $clog2(MH);
localparam integer SF_BITS = $clog2(SF);
localparam integer SF_NF_BITS = $clog2(SF*NF);
localparam integer N_REPS_BITS = $clog2(N_REPS);

logic [NF-1:0][WGT_ADDR_BITS-1:0] offsets;

typedef enum logic {ST_WR_0, ST_WR_1} state_wr_t;
typedef enum logic {ST_RD_0, ST_RD_1} state_rd_t;
typedef logic [NF_BITS:0] nf_t;
typedef logic [MH_BITS:0] sf_wr_t;
typedef logic [SF_NF_BITS:0] sf_rd_t;
typedef logic [N_REPS_BITS:0] reps_t;
typedef logic [NF_BITS-1:0] nf_t;
typedef logic [SF_BITS-1:0] sf_t;
typedef logic [SIMD_BITS-1:0] simd_t;
typedef logic [SF_NF_BITS-1:0] sf_rd_t;
typedef logic [N_REPS_BITS-1:0] reps_t;

// ----------------------------------------------------------------------------
// Writer
Expand All @@ -127,8 +128,9 @@ typedef logic [N_REPS_BITS:0] reps_t;
// -- Regs
state_wr_t state_wr_C, state_wr_N;

simd_t curr_simd_C, curr_simd_N;
nf_t curr_nf_C, curr_nf_N;
sf_wr_t curr_sf_C, curr_sf_N;
sf_t curr_sf_C, curr_sf_N;

logic rd_0_C, rd_0_N;
logic rd_1_C, rd_1_N;
Expand Down Expand Up @@ -156,6 +158,7 @@ always_ff @( posedge clk ) begin : REG_PROC_WR

curr_nf_C <= 0;
curr_sf_C <= 0;
curr_simd_C <= 0;

rd_0_C <= 1'b0;
rd_1_C <= 1'b0;
Expand All @@ -165,6 +168,7 @@ always_ff @( posedge clk ) begin : REG_PROC_WR

curr_nf_C <= curr_nf_N;
curr_sf_C <= curr_sf_N;
curr_simd_C <= curr_simd_N;

rd_0_C <= rd_0_N;
rd_1_C <= rd_1_N;
Expand All @@ -177,10 +181,10 @@ always_comb begin : NSL_PROC_WR

case (state_wr_C)
ST_WR_0:
state_wr_N = ((curr_sf_C == MH - 1) && (curr_nf_C == NF - 1) && ivld && ~rd_0_C) ? ST_WR_1 : ST_WR_0;
state_wr_N = ((curr_simd_C == SIMD - 1) && (curr_sf_C == SF - 1) && (curr_nf_C == NF - 1) && ivld && ~rd_0_C) ? ST_WR_1 : ST_WR_0;

ST_WR_1:
state_wr_N = ((curr_sf_C == MH - 1) && (curr_nf_C == NF - 1) && ivld && ~rd_1_C) ? ST_WR_0 : ST_WR_1;
state_wr_N = ((curr_simd_C == SIMD - 1) && (curr_sf_C == SF - 1) && (curr_nf_C == NF - 1) && ivld && ~rd_1_C) ? ST_WR_0 : ST_WR_1;

endcase
end
Expand All @@ -189,20 +193,21 @@ end
always_comb begin : DP_PROC_WR
curr_nf_N = curr_nf_C;
curr_sf_N = curr_sf_C;
curr_simd_N = curr_simd_C;

rd_0_N = done_0 ? 1'b0 : rd_0_C;
rd_1_N = done_1 ? 1'b0 : rd_1_C;

irdy = 1'b0;

a_we_0 = 0;
a_addr_0 = offsets[curr_nf_C] + curr_sf_C[MH_BITS:SIMD_BITS];
a_addr_0 = offsets[curr_nf_C] + curr_sf_C;
for(int i = 0; i < PE; i++)
for(int j = 0; j < SIMD; j++)
a_data_in_0[i][j] = idat[i];

a_we_1 = 0;
a_addr_1 = offsets[curr_nf_C] + curr_sf_C[MH_BITS:SIMD_BITS];
a_addr_1 = offsets[curr_nf_C] + curr_sf_C;
for(int i = 0; i < PE; i++)
for(int j = 0; j < SIMD; j++)
a_data_in_1[i][j] = idat[i];
Expand All @@ -215,20 +220,18 @@ always_comb begin : DP_PROC_WR
if(ivld) begin
for(int i = 0; i < PE; i++) begin
for(int j = 0; j < SIMD; j++) begin
if(curr_sf_C[SIMD_BITS-1:0] == j) begin
if(curr_simd_C == j) begin
a_we_0[i][j] = '1;
end
end
end

curr_nf_N = (curr_nf_C == NF-1) ? 0 : curr_nf_C + 1;
curr_sf_N = (curr_nf_C == NF-1) ? curr_sf_C + 1 : curr_sf_C;
curr_nf_N = (curr_nf_C == NF-1) ? 0 : curr_nf_C + 1;
curr_simd_N = (curr_nf_C == NF-1) ? ((curr_simd_C == SIMD-1) ? 0 : curr_simd_C + 1) : curr_simd_C;
curr_sf_N = (curr_nf_C == NF-1) ? ((curr_simd_C == SIMD-1) ? ((curr_sf_C == SF-1) ? 0 : curr_sf_C + 1) : curr_sf_C) : curr_sf_C;

if((curr_sf_C == MH - 1) && (curr_nf_C == NF - 1)) begin
if((curr_simd_C == SIMD - 1) && (curr_sf_C == SF - 1) && (curr_nf_C == NF - 1)) begin
rd_0_N = 1'b1;

curr_nf_N = 0;
curr_sf_N = 0;
end
end
end
Expand All @@ -241,16 +244,17 @@ always_comb begin : DP_PROC_WR
if(ivld && ~rd_1_C) begin
for(int i = 0; i < PE; i++) begin
for(int j = 0; j < SIMD; j++) begin
if(curr_sf_C[SIMD_BITS-1:0] == j) begin
if(curr_simd_C == j) begin
a_we_1[i][j] = '1;
end
end
end

curr_nf_N = (curr_nf_C == NF-1) ? 0 : curr_nf_C + 1;
curr_sf_N = (curr_nf_C == NF-1) ? curr_sf_C + 1 : curr_sf_C;
curr_nf_N = (curr_nf_C == NF-1) ? 0 : curr_nf_C + 1;
curr_simd_N = (curr_nf_C == NF-1) ? ((curr_simd_C == SIMD-1) ? 0 : curr_simd_C + 1) : curr_simd_C;
curr_sf_N = (curr_nf_C == NF-1) ? ((curr_simd_C == SIMD-1) ? ((curr_sf_C == SF-1) ? 0 : curr_sf_C + 1) : curr_sf_C) : curr_sf_C;

if((curr_sf_C == MH - 1) && (curr_nf_C == NF - 1)) begin
if((curr_simd_C == SIMD - 1) && (curr_sf_C == SF - 1) && (curr_nf_C == NF - 1)) begin
rd_1_N = 1'b1;

curr_nf_N = 0;
Expand Down
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