fix DDR3

WEEE-Open · Oct 18, 2024 · 2aeeedd · 2aeeedd
1 parent c55442b
commit 2aeeedd
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/tests/parsers/test_alecase.py b/tests/parsers/test_alecase.py
@@ -50,7 +50,7 @@ def test_ram():
             "model": "CT102464BA160B.C16",
             "ram-ecc": "no",
             "ram-timings": "11-11-11-28",
-            "ram-type": "DDR3",
+            "ram-type": "ddr3",
             "sn": "1949761536",
             "type": "ram",
             "working": "yes",
@@ -62,7 +62,7 @@ def test_ram():
             "model": "CT102464BA160B.C16",
             "ram-ecc": "no",
             "ram-timings": "11-11-11-28",
-            "ram-type": "DDR3",
+            "ram-type": "ddr3",
             "sn": "2172780544",
             "type": "ram",
             "working": "yes",

diff --git a/tests/parsers/test_asdpc.py b/tests/parsers/test_asdpc.py
@@ -44,7 +44,7 @@ def test_ram():
     expect = [
         {
             "ram-ecc": "no",
-            "ram-type": "DDR3",
+            "ram-type": "ddr3",
             "brand": "G Skill Intl",
             "capacity-byte": 8589934592,
             "frequency-hertz": 1333000000,
@@ -55,7 +55,7 @@ def test_ram():
         },
         {
             "ram-ecc": "no",
-            "ram-type": "DDR3",
+            "ram-type": "ddr3",
             "brand": "G Skill Intl",
             "capacity-byte": 8589934592,
             "frequency-hertz": 1333000000,