Welcome to the Full-Adder Design project! 🎉 This repository demonstrates the implementation of a full-adder using Verilog, focusing on gate-level modeling and functional verification. A must-have resource for beginners exploring digital logic design! 💻✨
| File Name | Description |
|---|---|
| fa.v | Verilog module implementing the full-adder with gate-level modeling. |
| fa_tb.v | Testbench for full_adder.v to validate sum and carry functionality. |
| fa.vcd | Value Change Dump file generated after simulation for waveform analysis. |
| fa.vvp | Compiled simulation file created by Icarus Verilog. |
LICENSE |
MIT License details. |
The full_adder.v file implements the full-adder logic:
- Sum (S): Outputs the XOR of inputs A, B, and Carry-In (Cin).
- Carry-Out (Cout): Outputs the majority logic of inputs A, B, and Cin.
| A | B | Cin | Sum (S) | Carry-Out (Cout) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
The full_adder_tb.v file verifies the functionality of the full-adder through exhaustive test cases. Results are logged in the terminal and exported to a .vcd file for waveform analysis.
- Beginner-friendly gate-level design.
- Comprehensive testbench for thorough validation.
- Modular and readable Verilog code.
For a detailed guide on setting up simulations using Icarus Verilog and GTKWave, check out my Logic Gates Simulation Repository. It includes step-by-step instructions to compile, simulate, and visualize Verilog designs.
Contributions are always welcome! Feel free to fork, clone, and enhance this project. 🚀
📜 This project is licensed under the MIT License. See the LICENSE file for details.