Pinned Loading
-
2-to-1-Multiplexer-Design-Verilog
2-to-1-Multiplexer-Design-Verilog PublicGate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
Verilog
-
Full-Adder-Design-Verilog
Full-Adder-Design-Verilog PublicGate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
Verilog
-
Logic_gates
Logic_gates PublicSimulate and analyze fundamental logic gates using Icarus Verilog and GTKWave. This project provides a modular Verilog implementation and a comprehensive testbench for precise validation, offering …
Verilog
-
Half-Adder-Design-Verilog
Half-Adder-Design-Verilog PublicA compact Verilog project implementing a half-adder with gate-level modeling, featuring a detailed testbench for functional verification and simulation.
Verilog
-
Music-Player-using-Python
Music-Player-using-Python PublicA Python-based music player featuring a sleek GUI built with Tkinter and audio playback powered by Pygame. It includes playlist management, play/pause, stop, and navigation controls, offering a sea…
Python
-
2bit-Ripple-Carry-Adder-Verilog
2bit-Ripple-Carry-Adder-Verilog PublicA Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀
Verilog
If the problem persists, check the GitHub status page or contact support.