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UoB-HPC · Feb 6, 2025 · 6110bce · 6110bce
1 parent 0ec0b8d
commit 6110bce
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Showing 3 changed files with 12 additions and 7 deletions.
diff --git a/src/include/simeng/arch/aarch64/helpers/sve.hh b/src/include/simeng/arch/aarch64/helpers/sve.hh
@@ -1346,8 +1346,8 @@ std::array<uint64_t, 4> svePtrue(
 template <typename T>
 std::array<uint64_t, 4> svePtrue_counter(const uint16_t VL_bits) {
   // Predicate as counter is 16-bits and has the following encoding:
-  //    - Up to first 4 bits encode the element size (0b1, 0b10, 0b100, 0b1000
-  //    for b h s d respectively)
+  //    - Up to first 4 bits (named LSZ) encode the element size (0b1, 0b10,
+  //    0b100, 0b1000 for b h s d respectively)
   //            - bits 0->LSZ
   //    - Bits LSZ -> 14 represent a uint of the number of consecutive elements
   //    from element 0 that are active / inactive
@@ -1356,8 +1356,8 @@ std::array<uint64_t, 4> svePtrue_counter(const uint16_t VL_bits) {
   //    - Bit 15 represents the invert bit
   std::array<uint64_t, 4> out = {0, 0, 0, 0};
 
-  // Set invert bit to 1 and count to 0
-  // (The first 0 elements are FALSE)
+  // Set invert bit to 1 and count to 0 so that the first 0 elements are FALSE.
+  // This is how the spec defines all true to be encoded.
   out[0] |= 0b1000000000000000;
 
   // Set Element size field

diff --git a/src/lib/arch/aarch64/Instruction_decode.cc b/src/lib/arch/aarch64/Instruction_decode.cc
@@ -538,8 +538,7 @@ void Instruction::decode() {
     if (isInstruction(InsnType::isStoreData)) {
       // Identify store instruction group
       if ((AARCH64_REG_Z0 <= metadata_.operands[0].reg &&
-           metadata_.operands[0].reg <= AARCH64_REG_Z31) ||
-          metadata_.operands[0].reg == AARCH64_REG_ZT0) {
+           metadata_.operands[0].reg <= AARCH64_REG_Z31)) {
         setInstructionType(InsnType::isSVEData);
       } else if ((metadata_.operands[0].reg <= AARCH64_REG_S31 &&
                   metadata_.operands[0].reg >= AARCH64_REG_Q0) ||
@@ -549,7 +548,7 @@ void Instruction::decode() {
       } else if (metadata_.operands[0].is_vreg) {
         setInstructionType(InsnType::isVectorData);
       } else if ((metadata_.operands[0].reg >= AARCH64_REG_ZAB0 &&
-                  metadata_.operands[0].reg < AARCH64_REG_ZT0) ||
+                  metadata_.operands[0].reg <= AARCH64_REG_ZT0) ||
                  metadata_.operands[0].reg == AARCH64_REG_ZA) {
         setInstructionType(InsnType::isSMEData);
       }

diff --git a/test/regression/aarch64/instructions/sme.cc b/test/regression/aarch64/instructions/sme.cc
@@ -7,6 +7,8 @@ namespace {
 
 using InstSme = AArch64RegressionTest;
 
+#if SIMENG_LLVM_VERSION >= 14
+
 TEST_P(InstSme, add) {
   // uint32_T, vgx2, vecs with ZA
   RUN_AARCH64(R"(
@@ -1354,4 +1356,8 @@ INSTANTIATE_TEST_SUITE_P(AArch64, InstSme,
                          ::testing::ValuesIn(genCoreTypeSVLPairs(EMULATION)),
                          paramToString);
 
+#else
+GTEST_ALLOW_UNINSTANTIATED_PARAMETERIZED_TEST(InstSme);
+#endif
+
 }  // namespace