Skip to content

Commit

Permalink
fix(export): correct clock freq in info.yaml
Browse files Browse the repository at this point in the history
  • Loading branch information
urish committed May 22, 2024
1 parent 8487c60 commit 2d2d056
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/exportProject.ts
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ project:
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "" # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 31500000 # Clock frequency in Hz (or 0 if not applicable)
clock_hz: 25175000 # Clock frequency in Hz (or 0 if not applicable)
# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
Expand Down

0 comments on commit 2d2d056

Please sign in to comment.