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test: change default testbench license to Apache-2.0 docs #14: Commit b906f3d pushed by urish
May 30, 2024 14:14 25s main
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May 30, 2024 14:14 25s
suppress warning for unused inputs docs #13: Commit 2c112d6 pushed by urish
May 27, 2024 12:33 23s main
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May 27, 2024 12:33 23s
docs: twitter account link docs #12: Commit 7a4440c pushed by urish
May 12, 2024 20:01 24s main
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May 12, 2024 20:01 24s
ci(fpga): experimental FPGA bitstream action docs #11: Commit 67f5971 pushed by urish
May 2, 2024 08:41 32s main
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May 2, 2024 08:41 32s
ci(fpga): experimental FPGA bitstream action docs #10: Commit 33f31df pushed by urish
May 2, 2024 08:41 31s main
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May 2, 2024 08:41 31s
Update README.md docs #9: Commit 6229636 pushed by mattvenn
April 28, 2024 18:25 28s main
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April 28, 2024 18:25 28s
docs: explain the "ena" pin better docs #8: Commit 4bc03dd pushed by urish
April 22, 2024 06:47 25s main
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April 22, 2024 06:47 25s
docs: link to explain about custom clock config docs #7: Commit da3fd6a pushed by urish
April 20, 2024 19:43 24s main
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April 20, 2024 19:43 24s
fix: disable "MAGIC_DEF_LABELS" in config.tcl docs #6: Commit 3bb2b5b pushed by urish
April 20, 2024 19:39 22s main
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April 20, 2024 19:39 22s
Update README.md docs #5: Commit 53c0d23 pushed by mattvenn
April 19, 2024 18:05 25s main
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April 19, 2024 18:05 25s
TT07 Verilog Project Template docs #4: Commit 3d8eb83 pushed by urish
April 19, 2024 17:56 25s main
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April 19, 2024 17:56 25s
TT07 Verilog Project Template docs #3: Commit 08d98e2 pushed by urish
April 19, 2024 17:48 23s main
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April 19, 2024 17:48 23s
TT07 Verilog Project Template docs #2: Commit 1528e05 pushed by urish
April 19, 2024 17:47 25s main
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April 19, 2024 17:47 25s
TT07 Verilog Project Template docs #1: Commit 46172fb pushed by urish
April 19, 2024 17:45 22s main
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April 19, 2024 17:45 22s