moved u* ports to pins for access during boot, moved config ini to ne…

…w naming, direction actions fixes

bin/migratev2.py

@@ -46,12 +46,12 @@
     ('(return\s+|=)\s*([^\s]+)\.output_byte', '\g<1> \g<2>.uo_out.value'),
     ('\.output_byte', '.uo_out.value'),
     # order matters
-    ('\.bidir_byte\s*=', '.uio_out.value ='),
-    ('(return\s+|=)\s*([^\s]+)\.bidir_byte', '\g<1> \g<2>.uio_in.value'),
-    ('([^\s]+)\.bidir_byte', '\g<1>.uio_in.value'),
+    ('\.bidir_byte\s*=', '.uio_in.value ='),
+    ('(return\s+|=)\s*([^\s]+)\.bidir_byte', '\g<1> \g<2>.uio_out.value'),
+    ('([^\s]+)\.bidir_byte', '\g<1>.uio_out.value'),
     ('\.bidir_mode', '.uio_oe[:]'), #
     ('\.project_nrst', '.rst_n'),
-    ('\.project_clk', '.clk')
+    ('\.project_clk([^_]+)', '.clk\g<1>')
 ]
 
 
@@ -177,4 +177,4 @@ def main():
 main()
 
 
-
+

src/config.ini

@@ -42,7 +42,7 @@ rp_clock_frequency = 125e6
 # connected to the demoboard.  If you want to bypass this step and
 # manually set the shuttle, uncomment this and set the option to
 # a valid shuttle
-# force_shuttle = tt05
+# force_shuttle = tt06
 
 
 # force_demoboard
@@ -56,19 +56,19 @@ rp_clock_frequency = 125e6
 [tt_um_test]
 clock_frequency = 10
 start_in_reset = no
-input_byte = 1
+ui_in = 1
 
 [tt_um_factory_test]
 clock_frequency = 10
 start_in_reset = no
-input_byte = 1
+ui_in = 1
 
 
 [tt_um_psychogenic_neptuneproportional]
 # set clock to 4kHz
 clock_frequency = 4000
 # clock config 4k, disp single bits
-input_byte = 0b11001000
+ui_in = 0b11001000
 mode = ASIC_RP_CONTROL
 
 
@@ -80,7 +80,7 @@ mode = ASIC_RP_CONTROL
 [tt_um_seven_segment_seconds]
 rp_clock_frequency = 120e6
 clock_frequency = 10e6
-input_byte = 0
+ui_in = 0
 mode = ASIC_RP_CONTROL
 
 
@@ -89,14 +89,14 @@ mode = ASIC_RP_CONTROL
 [tt_um_loopback]
 # ui_in[0] == 1 means bidirs on output
 clock_frequency = 1000
-input_byte = 1
+ui_in = 1
 
-# bidir_direction, 1 bit means we will
+# uio_oe_pico, 1 bit means we will
 # write to it (RP pin is output), 
 # 0 means read from (RP is input)
 # set to all output
-bidir_direction = 0xff
-bidir_byte = 0b110010101
+uio_oe_pico = 0xff
+uio_in = 0b110010101
 
 [tt_um_vga_clock]
 rp_clock_frequency = 126e6
@@ -113,20 +113,20 @@ mode = ASIC_MANUAL_INPUTS
 mode = ASIC_RP_CONTROL
 
 # start inactive (all ins 0)
-input_byte = 0
+ui_in = 0
 
 # Ensure we are *reading* from all of the ASIC's bidir pins, 
 # so bidirs all inputs:
-bidir_direction = 0
+uio_oe_pico = 0
 
 
 
 [tt_um_psychogenic_shaman]
 mode = ASIC_RP_CONTROL
 clock_frequency = 1e6
 # shaman uses a mix of in and out on bidir
-bidir_direction = 0b11001100
-bidir_byte = 0
+uio_oe_pico = 0b11001100
+uio_in = 0
 
 
 

src/first_boot.ini

@@ -24,18 +24,6 @@ command = setup_somehow()
 
 
 ## TESTS ##
-
-[run_01_bidir_test]
-message = Basic comms, mux, bidir and output pin test
-command = test_bidirs_03p5(0xff)
-shuttle = tt03p5
-
-
-[run_test_clocking_tt03p5]
-message = Test clocking a project manual style
-command = test_clocking(False, 128, 1)
-shuttle = tt03p5
-
 [run_test_clocking_tt04]
 message = TT04 factory test
 command = test_clocking(True, 128, 1)
@@ -46,6 +34,11 @@ message = TT05 factory test
 command = test_clocking(True, 128, 1)
 shuttle = tt05
 
+[run_test_clocking_tt06]
+message = TT06 factory test
+command = test_clocking(True, 128, 1)
+shuttle = tt06
+
 ## SUCCESS ##
 [onsuccess]
 # runs if all previous operations succeeded

src/tests/dffram.py

@@ -18,7 +18,7 @@ def __init__(self, pins:Pins):
             p.mode = Pins.OUT 
 
         self.p.ui_in.value = 0
-        self.p.uio_out.value = 0
+        self.p.uio_in.value = 0
 
     @property 
     def we(self):
@@ -49,7 +49,7 @@ def data_in(self):
 
     @data_in.setter
     def data_in(self, v:int):
-        self.p.uio_out.value = v        
+        self.p.uio_in.value = v        
 
 
 

src/tests/sram.py

@@ -30,7 +30,7 @@ def __init__(self, pins:Pins):
             p.mode = Pins.OUT 
 
         self.p.ui_in.value = 0
-        self.p.uio_out.value = 0
+        self.p.uio_in.value = 0
 
     @property 
     def bank_select(self):
@@ -68,19 +68,19 @@ def addr_high_in(self):
 
     @addr_high_in.setter 
     def addr_high_in(self, v:int):
-        self.p.uio_out.value = (self.p.uio_in.value & ~0x1f) | (v & 0x1f)
+        self.p.uio_in.value = (self.p.uio_in.value & ~0x1f) | (v & 0x1f)
 
     @property 
     def data_out(self):
         return  self.p.uo_out.value
 
     @property 
     def data_in(self):
-        return  self.p.uio_in.value
+        return  self.p.uio_out.value
 
     @data_in.setter
     def data_in(self, v:int):
-        self.p.uio_out.value = v        
+        self.p.uio_in.value = v        
 
 
 
@@ -173,4 +173,4 @@ def test():
     return tt, sram
 
 
-
+

src/ttboard/boot/firstboot_operations.py

@@ -109,16 +109,16 @@ def say_hello(delay_interval_ms:int=200, times:int=1):
         short_delay_ms = 10
     for _i in range(times):
         for v in hello_values:
-            tt.uio_out.value = v
+            tt.uio_in.value = v
             time.sleep_ms(delay_interval_ms - short_delay_ms)
 
-            tt.uio_out.value = 0
+            tt.uio_in.value = 0
             time.sleep_ms(short_delay_ms)
 
-        tt.uio_out.value = 0
+        tt.uio_in.value = 0
         time.sleep_ms(short_delay_ms * 3)
 
     tt.clock_project_stop()
 
-    tt.uio_oe[:] = [Pins.IN] * 8 # reset to inputs, optional but polite
+    tt.uio_oe_pico[:] = [Pins.IN] * 8 # reset to inputs, optional but polite
     return True

src/ttboard/boot/post.py

@@ -123,21 +123,20 @@ def test_bidirs(self) -> bool:
         self.tt.clock_project_PWM(auto_clock_freq) # clock it real good
 
         log.info('POST: starting bidirection pins tests')
-        self.tt.uio_oe[:] = [Pin.OUT] * 8
-        for bp in self.tt.bidirs:
-            bp(0) # start low
+        self.tt.uio_oe_pico[:] = [Pin.OUT] * 8
+        self.tt.uio_in.value = 0 # start all low
 
         errCount = 0
         for i in range(0xff):
-            self.tt.uio_out.value = i 
+            self.tt.uio_in.value = i 
             time.sleep_ms(update_delay_ms)
             outbyte = self.tt.uo_out.value
             if outbyte !=  i:
                 log.warn(f'MISMATCH between bidir val {i} and output {outbyte}')
                 errCount += 1
 
         # reset everything
-        self.tt.uio_oe[:] = [Pin.IN] * 8
+        self.tt.uio_oe_pico[:] = [Pin.IN] * 8
 
         self.tt.clock_project_stop()
         self.tt.mode = curMode

src/ttboard/config/user_config.py

@@ -7,7 +7,6 @@
 import gc
 from ttboard.config.parser import ConfigParser
 from ttboard.mode import RPMode
-from ttboard.config.config_file import ConfigFile
 
 import ttboard.log as logging
 log = logging.getLogger(__name__)
@@ -22,15 +21,15 @@ class UserProjectConfig:
             # set clock to 4kHz
             clock_frequency = 4000
             # clock config 4k, disp single bits
-            input_byte = 0b11001000
+            ui_in = 0b11001000
             mode = ASIC_RP_CONTROL
         
         You can use this to set:
             - mode (str)
             - start_in_reset (bool)
-            - input_byte (int)
-            - bidir_direction (int)
-            - bidir_byte (int)
+            - ui_in (int)
+            - uio_oe_pico (int)
+            - uio_in (int)
             - clock_frequency (int) project clock
             - rp_clock_frequency (int) RP2040 system clock frequency
             
@@ -40,9 +39,9 @@ class UserProjectConfig:
         see more info.
 
     '''
-    opts = ['mode', 'start_in_reset', 'input_byte',
-                         'bidir_direction',
-                         'bidir_byte',
+    opts = ['mode', 'start_in_reset', 'ui_in',
+                         'uio_oe_pico',
+                         'uio_in',
                          'clock_frequency',
                          'rp_clock_frequency']
 
@@ -154,7 +153,6 @@ def __init__(self, ini_filepath:str='config.ini'):
             val = None
             if conf.has_option('DEFAULT', opt):
                 val = conf.get('DEFAULT', opt)
-                print(f'DEFOPT {opt}: {val}')
             setattr(self, f'_{opt}', val)