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Update project tt_um_cdc_test (FangameEmpire/tt09-CDC-test) #437

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merged 1 commit into from
Nov 10, 2024
Merged

Update project tt_um_cdc_test (FangameEmpire/tt09-CDC-test) #437

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4 changes: 2 additions & 2 deletions projects/tt_um_cdc_test/commit_id.json
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@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/FangameEmpire/tt09-CDC-test",
"commit": "60d11dd4b6dd8726b98ab5b36919993f7ea69173",
"workflow_url": "https://github.com/FangameEmpire/tt09-CDC-test/actions/runs/11732407573",
"commit": "8fccc4042690f89b3df493d013ab4db8249621d5",
"workflow_url": "https://github.com/FangameEmpire/tt09-CDC-test/actions/runs/11765574996",
"sort_id": 1731042524553,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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40 changes: 20 additions & 20 deletions projects/tt_um_cdc_test/docs/info.md
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<!---

This file is used to generate your project datasheet. Please fill in the information below and delete any unused
sections.

You can also include images in this folder and reference them in the markdown. Each image must be less than
512 kb in size, and the combined size of all images must be less than 1 MB.
-->

## How it works

TBD - Need to determine bus size and ALU complexity

## How to test

TBD

## External hardware

TBD - Probably juust some clock generators and the carrier board for UART
<!---
This file is used to generate your project datasheet. Please fill in the information below and delete any unused
sections.
You can also include images in this folder and reference them in the markdown. Each image must be less than
512 kb in size, and the combined size of all images must be less than 1 MB.
-->
## How it works
If you're seeing this, I couldn't the Clock Domain Crossing project running. This is just a TT08 demo again.
## How to test
Runs automaticaly.
## External hardware
VGA PMOD on UO.
111 changes: 56 additions & 55 deletions projects/tt_um_cdc_test/info.yaml
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# Tiny Tapeout project information
project:
title: "Clock Domain Crossing Test" # Project title
author: "Nicklaus Thompson" # Your name
discord: "fangameempire" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "A ring of ALUs separated by CDCs" # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)

# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

# Your top module name must start with "tt_um_". Make it unique by including your github username:
top_module: "tt_um_cdc_test"

# List your project's source files here.
# Source files must be in ./src and you must list each source file separately, one per line.
# Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
source_files:
- "project.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: ""
ui[1]: ""
ui[2]: ""
ui[3]: "RX"
ui[4]: ""
ui[5]: ""
ui[6]: ""
ui[7]: ""

# Outputs
uo[0]: ""
uo[1]: ""
uo[2]: ""
uo[3]: ""
uo[4]: "TX"
uo[5]: ""
uo[6]: ""
uo[7]: ""

# Bidirectional pins
uio[0]: ""
uio[1]: ""
uio[2]: ""
uio[3]: ""
uio[4]: ""
uio[5]: ""
uio[6]: ""
uio[7]: ""

# Do not change!
yaml_version: 6
# Tiny Tapeout project information
project:
title: "SkyKing Demo" # Project title
author: "Nicklaus Thompson" # Your name
discord: "fangameempire" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "Types some text over an image of a plane flying into the sunset" # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 25200000 # Clock frequency in Hz (or 0 if not applicable)

# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

# Your top module name must start with "tt_um_". Make it unique by including your github username:
top_module: "tt_um_cdc_test"

# List your project's source files here.
# Source files must be in ./src and you must list each source file separately, one per line.
# Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
source_files:
- "project.v"
- "hvsync_generator.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: ""
ui[1]: ""
ui[2]: ""
ui[3]: ""
ui[4]: ""
ui[5]: ""
ui[6]: ""
ui[7]: ""

# Outputs
uo[0]: "HS"
uo[1]: "R0"
uo[2]: "G0"
uo[3]: "B0"
uo[4]: "VS"
uo[5]: "R1"
uo[6]: "G1"
uo[7]: "B1"

# Bidirectional pins
uio[0]: ""
uio[1]: ""
uio[2]: ""
uio[3]: ""
uio[4]: ""
uio[5]: ""
uio[6]: ""
uio[7]: ""

# Do not change!
yaml_version: 6
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